A thermosetting sheet according to the present invention includes a thermosetting resin and a thermoplastic resin, in which a thickness change rate when a temperature is changed from 25° C. to 200° C. is 0% or more and 10% or less.

A thermosetting sheet according to the present invention includes a thermosetting resin and a thermoplastic resin, in which a thickness change rate when a temperature is changed from 25° C. to 200° C. is 0% or more and 10% or less.

A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.

A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.

A mounting apparatus includes: a bonding stage; a base; a mounting head for performing a temporary press-attachment process in which semiconductor chips are suction-held and temporarily press-attached to a mounted object and a final press-attachment process in which the temporarily press-attached semiconductor chips are finally press-attached; a film arrangement mechanism arranged on the bonding stage or the base; and a controller which controls driving of the mounting head and the film arrangement mechanism. The film arrangement mechanism includes: a film feed-out mechanism which has a pair of feed rollers with a cover film extended there-between and successively feeds out a new cover film; and a film movement mechanism which moves the cover film in a horizontal direction with respect to a substrate.

A mounting apparatus includes: a bonding stage; a base; a mounting head for performing a temporary press-attachment process in which semiconductor chips are suction-held and temporarily press-attached to a mounted object and a final press-attachment process in which the temporarily press-attached semiconductor chips are finally press-attached; a film arrangement mechanism arranged on the bonding stage or the base; and a controller which controls driving of the mounting head and the film arrangement mechanism. The film arrangement mechanism includes: a film feed-out mechanism which has a pair of feed rollers with a cover film extended there-between and successively feeds out a new cover film; and a film movement mechanism which moves the cover film in a horizontal direction with respect to a substrate.

Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.

Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.