A method for integrating III-V semiconductor materials onto a rigid host substrate deposits a thin layer of reactive metal film on the rigid host substrate. The layer can also include a separation layer of unreactive metal or dielectric, and can be patterned. The unreactive metal pattern can create self-aligned device contacts after bonding is completed. The III-V semiconductor material is brought into contact with the thin layer of reactive metal. Bonding is by a low temperature heat treatment under a compressive pressure. The reactive metal and the functional semiconductor material are selected to undergo solid state reaction and form a stable alloy under the low temperature heat treatment without degrading the III-V material. A semiconductor device of the invention includes a functional III-V layer bonded to a rigid substrate via an alloy of a component of the functional III-V layer and a metal that bonds to the rigid substrate.

An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically insulating adhesive base layer, or a structure wherein an electrically insulating adhesive base layer and an electrically insulating adhesive cover layer are laminated together and the electrically conductive particles are disposed near the interface therebetween. Electrically conductive particle groups configured from two or more electrically conductive particles are disposed in a lattice point region of a planar lattice pattern. A preferred lattice point region is a circle centered on a lattice point. A radius of the circle is not less than two times and not more than seven times the average particle diameter of the electrically conductive particles.

A method for cohesively connecting a first component of a power semiconductor module to a second component of a power semiconductor module by sintering, the method comprising the steps of: applying a layer of unsintered sinter material to a predetermined bonding surface of the first component, arranging the second component on the surface layer of unsintered sinter material, attaching the second component to the first component by applying pressure and/or temperature on a locally delimited partial area within the predetermined bonding surface, processing the first and/or second component and/or other components of the power semiconductor module, and complete-area sintering of the sinter material.

A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

An adhesive for a semiconductor, comprising an epoxy resin, a curing agent, and a compound having a group represented by the following formula (1): ##STR00001##
wherein R.sup.1 represents an electron-donating group.

A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.

A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.

An electronic device structure and a method for making an electronic device. As non-limiting examples, various aspects of this disclosure provide a method of manufacturing an electronic device that comprises the utilization of a carrier assisted substrate, and an electronic device manufactured thereby.

The present disclosure provides a method of transferring an electronic element using a stamping and magnetic field alignment technology and an electronic device including an electronic element transferred using the method. In the present disclosure, a polymer may be simultaneously coated on a plurality of electronic elements using the stamping process, and the polymer may be actively coated on the electronic elements without restrictions on process parameters such as size and spacing of the electronic elements. Moreover, the self-aligned ferromagnetic particles have an anisotropic current flow through which current flows only in the aligned direction. Therefore, the current may flow only vertically between the electronic element and the electrode, and there is no electrical short circuit between a peripheral LED element and the electrode.