A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.

Provided is a semiconductor package, including a lower semiconductor chip, a plurality of semiconductor chips that are disposed on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip, a plurality of nonconductive layers disposed between the plurality of semiconductor chips, a nonconductive pattern that extends from the nonconductive layers and is disposed on lateral surfaces of at least one of the plurality of semiconductor chips, a first mold layer disposed a top surface of the nonconductive pattern, and a second mold layer disposed a lateral surface of the nonconductive pattern and a lateral surface of the first mold layer, wherein the nonconductive pattern and the first mold layer are disposed between the second mold layer and lateral surfaces of the plurality of semiconductor chips.

Embodiments disclose a package structure and a fabricating method. The package structure includes: a semiconductor chip; a first non-conductive layer covering a front surface of the semiconductor chip and part of a side wall of the semiconductor chip; a second non-conductive layer positioned on an upper surface of the first non-conductive layer and covering at least part of a side wall of the first non-conductive layer, wherein a melt viscosity of the first non-conductive layer is greater than a melt viscosity of the second non-conductive layer; a substrate; and a solder mask layer positioned on a surface of the substrate, where a first opening is provided in the solder mask layer. The semiconductor chip is flip-chip bonded on the substrate, a surface of the second non-conductive layer away from the first non-conductive layer and a surface of the solder mask layer away from the substrate are bonding surfaces.

A die placement system provides a tip body and die placement head to ensure planarity of a die to substrate without the need for calibration prior to each pick and place operation. A self-aligning tip incorporated into a tip body aids in die placement/attachment. This tip provides for global correction of planarity errors that exist between a die and substrate, regardless of whether those errors stem from gantry (i.e. die-side misalignment) or machine deck tool (i.e. substrate-side misalignment) misalignment.

A die placement system provides a tip body and die placement head to ensure planarity of a die to substrate without the need for calibration prior to each pick and place operation. A self-aligning tip incorporated into a tip body aids in die placement/attachment. This tip provides for global correction of planarity errors that exist between a die and substrate, regardless of whether those errors stem from gantry (i.e. die-side misalignment) or machine deck tool (i.e. substrate-side misalignment) misalignment.

Methods for attachment and devices produced using such methods are disclosed. In certain examples, the method comprises disposing a capped nanomaterial on a substrate, disposing a die on the disposed capped nanomaterial, drying the disposed capped nanomaterial and the disposed die, and sintering the dried disposed die and the dried capped nanomaterial at a temperature of 300° C. or less to attach the die to the substrate. Devices produced using the methods are also described.

Methods for attachment and devices produced using such methods are disclosed. In certain examples, the method comprises disposing a capped nanomaterial on a substrate, disposing a die on the disposed capped nanomaterial, drying the disposed capped nanomaterial and the disposed die, and sintering the dried disposed die and the dried capped nanomaterial at a temperature of 300° C. or less to attach the die to the substrate. Devices produced using the methods are also described.

To provide a wound body of a sheet for sintering bonding with a base material that realizes a satisfactory operational efficiency in a process of producing a semiconductor device comprising sintering bonding portions of semiconductor chips and that also has both a satisfactory storage stability and a high storage efficiency. A wound body 1 according to the present invention has a form in which a sheet for sintering bonding with a base material X is wound around a winding core 2 into a roll shape, the sheet for sintering bonding with a base material X having a laminated structure comprising: a base material 11; and a sheet for sintering bonding 10, comprising an electrically conductive metal containing sinterable particle and a binder component.

To provide a wound body of a sheet for sintering bonding with a base material that realizes a satisfactory operational efficiency in a process of producing a semiconductor device comprising sintering bonding portions of semiconductor chips and that also has both a satisfactory storage stability and a high storage efficiency. A wound body 1 according to the present invention has a form in which a sheet for sintering bonding with a base material X is wound around a winding core 2 into a roll shape, the sheet for sintering bonding with a base material X having a laminated structure comprising: a base material 11; and a sheet for sintering bonding 10, comprising an electrically conductive metal containing sinterable particle and a binder component.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.