An illumination device includes a supporting base, and a light-emitting element inserted in the supporting base. The light-emitting element includes a substrate having a supporting surface and a side surface, a light-emitting chip disposed on the supporting surface, and a first wavelength conversion layer covering the light-emitting chip and only a portion of the supporting surface without covering the side surface.

A package includes a carrier substrate, a first die, and a second die. The first die and the second die are stacked on the carrier substrate in sequential order. The first die includes a first bonding layer, a second bonding layer, and an alignment mark embedded in the first bonding layer. The second die includes a third bonding layer. A surface of the first bonding layer form a rear surface of the first die and a surface of the second bonding layer form an active surface of the first die. The rear surface of the first die is in physical contact with the carrier substrate. The active surface of the first die is in physical contact with the third bonding layer of the second die.

A package includes a carrier substrate, a first die, and a second die. The first die and the second die are stacked on the carrier substrate in sequential order. The first die includes a first bonding layer, a second bonding layer, and an alignment mark embedded in the first bonding layer. The second die includes a third bonding layer. A surface of the first bonding layer form a rear surface of the first die and a surface of the second bonding layer form an active surface of the first die. The rear surface of the first die is in physical contact with the carrier substrate. The active surface of the first die is in physical contact with the third bonding layer of the second die.

An integrated circuit device assembly including a graphene-coated heat spreader, including: a substrate; a die coupled to the substrate; and a heat spreader thermally coupled to the die, the heat spreader comprising: a body of thermally conductive metal defining a cavity at least partially surrounding the die; and a graphene layer contacting a surface of the body.

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.

A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.

A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.