A method of manufacturing a chip module comprises a step of disposing a first electronic element 13 on a first jig 500, a step of disposing a first connector 60 on the first electronic element 13 via a conductive adhesive 5, a step of disposing a second electronic element 23 on the first connector 60 via a conductive adhesive 5, a step of disposing a second connector 70 on a second jig 550, a step of reversing the second jig in a state where the second connector 70 is fixed to the second jig 550 and disposing the second connector 70 on the second electronic element 23 via a conductive adhesive 5, and a step of curing the conductive adhesives 5.

A method includes performing a non-screen printing process that deposits solder on a lead frame or on conductive features of a semiconductor die or wafer, or on or in a conductive via of a laminate structure. The method further comprises engaging the semiconductor die to the lead frame, performing a thermal process that reflows the solder, performing a molding process that forms a package structure which encloses the semiconductor die and a portion of the lead frame, and separating a packaged electronic device from a remaining portion of the lead frame.

The present invention relates to a reel-to-reel layer reflow method, which emits a uniformized laser beam, which can easily adjust the emission area, and which is for the purpose of improving productivity. An embodiment of the present invention provides a reel-to-reel layer reflow method comprising the steps of: a) transferring a substrate, which has been wound in a roll type, to one side while unwinding the same; b) forming a solder portion on the substrate; c) seating an emission target element on the solder portion and seating a non-emission target element on the substrate; d) surface-emitting a laser beam to the solder portion, on which the emission target element is seated, such that the emission target element is attached to the substrate; e) inspecting the substrate structure manufactured through said step d); and f) winding the substrate structure in a roll type.

A circuit backplane of a display panel, a method for manufacturing the same, and a display panel are provided. The circuit backplane includes a substrate and a plurality of circuit regions on the substrate. Each of the plurality of circuit regions includes a cathode soldered electrode, an anode soldered electrode, and a flow blocking island that are on the substrate. The flow blocking island is between the cathode soldered electrode and the anode soldered electrode, and in a thickness direction of the circuit backplane, a height of the flow blocking island is greater than each of a height of the cathode soldered electrode and a height of the anode soldered electrode.

A method produces a plurality of optoelectronic modules, and includes: A) providing a metallic carrier assembly with a plurality of carrier units; B) applying a logic chip, each having at least one integrated circuit, to the carrier units; C) applying emitter regions that generate radiation, which can be individually electrically controlled; D) covering the emitter regions and the logic chips with a protective material; E) overmolding the emitter regions and the logic chips so that a cast body is formed, which joins the carrier units, the logic chips and the emitter regions to one another; F) removing the protective material and applying electrical conductor paths to the upper sides of the logic chips and to a cast body upper side; and G) dividing the carrier assembly into the modules.

A method produces a plurality of optoelectronic modules, and includes: A) providing a metallic carrier assembly with a plurality of carrier units; B) applying a logic chip, each having at least one integrated circuit, to the carrier units; C) applying emitter regions that generate radiation, which can be individually electrically controlled; D) covering the emitter regions and the logic chips with a protective material; E) overmolding the emitter regions and the logic chips so that a cast body is formed, which joins the carrier units, the logic chips and the emitter regions to one another; F) removing the protective material and applying electrical conductor paths to the upper sides of the logic chips and to a cast body upper side; and G) dividing the carrier assembly into the modules.

A semiconductor device includes: a semiconductor element; a joined member that is joined to the semiconductor element and includes a nickel film; and a joining layer that is joined to the joined member and contains 2.0 wt % or higher of copper, in which the joining layer includes a solder portion and a Cu.sub.6Sn.sub.5 portion, base metal of the solder portion contains at least tin as a constituent element and contains elemental copper, and the Cu.sub.6Sn.sub.5 portion is in contact with the nickel film.

Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

A second lead frame is set onto a conductive layer and a busbar. The second lead frame has holes previously formed at opposite ends thereof, and pieces of solder material or solder pieces are inserted into the holes. Then, the solder pieces are vibrated by an ultrasonically vibrating tool, whereby the solder pieces are melted without having a high temperature. The second lead frame is thus bonded to the conductive layer and the busbar. A semiconductor element and the busbar are connected by a first lead frame and the second lead frame. The connection structure thereof is such that the second lead frame to be bonded by ultrasonic bonding or other bonding methods is not directly in contact with the semiconductor element, which eliminates the risk of damage to the semiconductor element.