A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.

A power field-effect transistor package is fabricated. A leadframe including a flat plate and a coplanar flat strip spaced from the plate is provided. The plate has a first thickness and the strip has a second thickness smaller than the first thickness. A field-effect power transistor chip having a third thickness is provided. A first and second contact pad on one chip side and a third contact pad on the opposite chip side are created. The first pad is attached to the plate and the second pad to the strip. Terminals are concurrently attached to the plate and the strip so that the terminals are coplanar with the third contact pad. The thickness difference between plate and strip and spaces between chip and terminals is filled with an encapsulation compound having a surface coplanar with the plate and the opposite surface coplanar with the third pad and terminals. The chip, leadframe and terminals are integrated into a package having a thickness equal to the sum of the first and third thicknesses.

A connector for coupling an electronic component having an external connector pad to another structure, comprising an anisotropic conductive elastomer or adhesive composite comprising a plurality of separate columns of conductive particles held in an insulating matrix, with a top particle exposed to a surface of the matrix, wherein at least the top particle is coated with a metal that can permanently bond to the connector pad of the electronic component. Also disclosed are a related method, and a related electronic assembly.

A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.

Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use a film during fabrication to control the distribution of an under-fill material between one or more components and a packaging substrate. The method includes mounting components to a first side of a packaging substrate and applying a film to a second side of a packaging substrate. The method also includes mounting a lower component to the second side of the packaging substrate and under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent. The method also includes removing the film on the second side of the packaging substrate and mounting solder balls to the second side of the packaging substrate after removal of the film.

A semiconductor device includes a substrate, a semiconductor element, a terminal and a solder outflow prevention part. The semiconductor element is fixed on one side of the substrate via a first solder layer. The terminal that is fixed on the one side of the substrate via a second solder layer. The solder outflow prevention part is formed between the semiconductor element and the terminal in the one side of the substrate and is configured to prevent the first solder layer and the second solder layer from outflowing. A distance between the solder outflow prevention part and the semiconductor element is longer than a thickness of the first solder layer.

A semiconductor device includes a substrate, a semiconductor element, a terminal and a solder outflow prevention part. The semiconductor element is fixed on one side of the substrate via a first solder layer. The terminal that is fixed on the one side of the substrate via a second solder layer. The solder outflow prevention part is formed between the semiconductor element and the terminal in the one side of the substrate and is configured to prevent the first solder layer and the second solder layer from outflowing. A distance between the solder outflow prevention part and the semiconductor element is longer than a thickness of the first solder layer.

A semiconductor device may be provided with: a semiconductor chip; an encapsulant encapsulating the semiconductor chip therein; and a conductor member joined to the semiconductor chip via a solder layer within the encapsulant. The conductor member may comprise a joint surface in contact with the solder layer and a side surface extending from a peripheral edge of the joint surface. The side surface may comprise an unroughened area and a roughened area that is greater in surface roughness than the unroughened area. The unroughened area may be located adjacent to the peripheral edge of the joint surface.

A bonding structure bonds a Cu wiring line and a device electrode with each other. The bonding structure is arranged between the Cu wiring line and the device electrode, and comprises a first intermetallic compound (IMC) layer (a layer of an intermetallic compound of Cu and Sn) formed on the interface with the Cu wiring line, a second intermetallic compound (IMC) layer (a layer of an intermetallic compound of Cu and Sn) formed on the interface with the device electrode, and an intermediate layer that is present between the intermetallic compound layers. In the intermediate layer, a network-like IMC (a network-like intermetallic compound of Cu and Sn) is present in Sn.

Selective transfer of dies including semiconductor devices to a target substrate can be performed employing local laser irradiation. Coining of at least one set of solder material portions can be employed to provide a planar surface-to-surface contact and to facilitate bonding of adjoining pairs of bond structures. Laser irradiation on the solder material portions can be employed to sequentially bond selected pairs of mated bonding structures, while preventing bonding of devices not to be transferred to the target substrate. Additional laser irradiation can be employed to selectively detach bonded devices, while not detaching devices that are not bonded to the target substrate. The transferred devices can be pressed against the target substrate during a second reflow process so that the top surfaces of the transferred devices can be coplanar. Wetting layers of different sizes can be employed to provide a trapezoidal vertical cross-sectional profile for reflowed solder material portions.