A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.

Provided relates to a method for manufacturing an anisotropic conductive adhesive and a method for mounting a component using an anisotropic conductive adhesive, and provides a method for manufacturing an anisotropic conductive adhesive, including: a process of removing a first oxide film on solder particles by using a first reducing agent; and a process of manufacturing an anisotropic conductive adhesive by mixing the solder particles, a gapper, and an adhesive resin.

Provided relates to a method for manufacturing an anisotropic conductive adhesive and a method for mounting a component using an anisotropic conductive adhesive, and provides a method for manufacturing an anisotropic conductive adhesive, including: a process of removing a first oxide film on solder particles by using a first reducing agent; and a process of manufacturing an anisotropic conductive adhesive by mixing the solder particles, a gapper, and an adhesive resin.

Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.

A semiconductor package includes a semiconductor chip that includes a first region and a second region spaced apart from the first region; a plurality of connection bumps disposed under the first region of the semiconductor chip; and a protection layer that covers a bottom surface of the semiconductor chip in the second region, wherein the protection layer does not cover the bottom surface of the semiconductor chip in the first region and is not disposed between the plurality of connection bumps. The semiconductor chip of the semiconductor package is protected by the protection layer.

Method for manufacturing an RFID tag comprising an IC and an antenna. The method comprising the steps of providing an antenna made of a soldering material, which antenna is at least partly covered with a hot melt adhesive in solid form; heating the antenna to a temperature above its melting point, wherein the heated parts of the antenna and the hot melt adhesive melt, placing an IC in a predetermined position which position is suitable for the IC to connect to the antenna; pressing the IC and antenna together, such that, an electrical connection between the IC and the antenna is established; and cooling RFID tag, such that the hot melt adhesive and the antenna solidify, wherein a soldered joint between the IC and the antenna is achieved and the hot melt adhesive surrounds the joint between the IC and the antenna.

The present disclosure relates to an adhesive resin composition for bonding semiconductors, including: a thermoplastic resin; a thermosetting resin; a curing agent; and a compound having a specific structure, and an adhesive film for semiconductors including the same.

The present disclosure relates to an adhesive resin composition for bonding semiconductors, including: a thermoplastic resin; a thermosetting resin; a curing agent; and a compound having a specific structure, and an adhesive film for semiconductors including the same.