The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

An anisotropic conductive film in which conductive particles are disposed in an insulating resin layer has a particle disposition of the conductive particles such that a first orthorhombic lattice region being formed by arranging a plurality of arrangement axes of the conductive particles, disposed in an a direction at a predetermined pitch, in a b direction inclined with respect to the a direction at an angle, and a second orthorhombic lattice region being formed by arranging a plurality of arrangement axes of the conductive particles, disposed in the a direction at a predetermined pitch, in a c direction obtained by inverting the b direction with respect to the a direction are repeatedly disposed. Regardless of the shape of the terminal arrangements and the materials of electronic components, a good conduction state is ensured while the respective terminals hold conductive particles. Further, the occurrence of a short circuit is prevented.

An anisotropic conductive film in which conductive particles are disposed in an insulating resin layer has a particle disposition of the conductive particles such that a first orthorhombic lattice region being formed by arranging a plurality of arrangement axes of the conductive particles, disposed in an a direction at a predetermined pitch, in a b direction inclined with respect to the a direction at an angle, and a second orthorhombic lattice region being formed by arranging a plurality of arrangement axes of the conductive particles, disposed in the a direction at a predetermined pitch, in a c direction obtained by inverting the b direction with respect to the a direction are repeatedly disposed. Regardless of the shape of the terminal arrangements and the materials of electronic components, a good conduction state is ensured while the respective terminals hold conductive particles. Further, the occurrence of a short circuit is prevented.

An alignment mark at a position that overlaps an area in which an anisotropic conductive film is pasted, and to accurately perform alignment using an image captured by a camera. An alignment method in which an electronic component is mounted on the obverse surface of a transparent substrate with a conductive adhesive agent interposed therebetween, a substrate-side alignment mark and a component-side alignment mark are adjusted from the captured image, and the position at which the electronic component is mounted on the transparent substrate is aligned, wherein in the conductive adhesive agent, conductive particles are in a regular arrangement as viewed from a planar perspective, and in the captured image, the outside edges of the alignment marks exposed between the conductive particles are intermittently visible as line segments (S) along the imaginary line segments of the outside edges of the alignment mark.

An alignment mark at a position that overlaps an area in which an anisotropic conductive film is pasted, and to accurately perform alignment using an image captured by a camera. An alignment method in which an electronic component is mounted on the obverse surface of a transparent substrate with a conductive adhesive agent interposed therebetween, a substrate-side alignment mark and a component-side alignment mark are adjusted from the captured image, and the position at which the electronic component is mounted on the transparent substrate is aligned, wherein in the conductive adhesive agent, conductive particles are in a regular arrangement as viewed from a planar perspective, and in the captured image, the outside edges of the alignment marks exposed between the conductive particles are intermittently visible as line segments (S) along the imaginary line segments of the outside edges of the alignment mark.

The invention concerns a process for the production of a circuit carrier (1) equipped with at least one surface-mount LED (SMD-LED), wherein the at least one SMD-LED (2) is positioned in oriented relationship to one or more reference points (3) of the circuit carrier (1) on the circuit carrier (1), wherein the position of a light-emitting region (4) of the at least one SMD-LED (2) is optically detected in the SMD-LED (2) and the at least one SMD-LED (2) is mounted to the circuit carrier (1) in dependence on the detected position of the light-emitting region (4) of the at least one SMD-LED (2), and such a circuit carrier (1).

The invention concerns a process for the production of a circuit carrier (1) equipped with at least one surface-mount LED (SMD-LED), wherein the at least one SMD-LED (2) is positioned in oriented relationship to one or more reference points (3) of the circuit carrier (1) on the circuit carrier (1), wherein the position of a light-emitting region (4) of the at least one SMD-LED (2) is optically detected in the SMD-LED (2) and the at least one SMD-LED (2) is mounted to the circuit carrier (1) in dependence on the detected position of the light-emitting region (4) of the at least one SMD-LED (2), and such a circuit carrier (1).

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

The present invention provides a method for manufacturing an LED display including a wiring board and LEDs arranged at a constant distance from the wiring board. The method includes: aligning an LED substrate 1 having LEDs 11 with a wiring board 2, and pressing and joining the LED substrate onto the wiring board. Each LED has a bonding surface. The wiring board includes bonding layers. The aligning step is performed so that the bonding surfaces are joined on the bonding layers in the pressing and joining step. The method further includes: temporarily bonding the LEDs onto the wiring board by curing the bonding layers through irradiation with ultraviolet light UV; peeling off the LEDs from the LED substrate through irradiation with laser light L; and permanently bonding the LEDs onto the wiring board by heating the bonding layers of the LEDs so as to further cure the bonding layers.