The present disclosure relates generally to digital microphone and other sensor assemblies including a transducer and a delta-sigma analog-to-digital converter (ADC) with digital-to-analog converter (DAC) element mismatch shaping and more particularly to sensor assemblies and electrical circuits therefor including a dynamic element matching (DELM) entity configured to select DAC elements based on data weighted averaging (DWA) and a randomized non-negative shift.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

An analog signal processor includes a sampling unit configured to (i) filter, in the frequency domain, a received time domain analog signal into a low-frequency end of a corresponding frequency spectrum, (ii) sample the filtered analog signal at a frequency substantially higher than the low-frequency end, and (iii) spread quantization noise over an expanded Nyquist zone of the corresponding frequency spectrum. The processor further includes a noise shaping unit configured to shape the spread quantization noise out of the low-frequency end of the corresponding frequency spectrum such that the filtered analog signal and the shaped quantization noise are substantially separated in the frequency domain, and a quantization unit configured to apply delta-sigma modulation to the filtered analog signal using at least one quantization bit, and output a digitized bit stream that substantially follows the amplitude of the received time domain analog signal.

A quad signal generator circuit generates four 2.sup.N-1 bit control signals in response to a 2.sup.N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2.sup.N-1 bit control signals. Outputs of the 2.sup.N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2.sup.N-1 bit thermometer coded signal and a time delay applied to the 2.sup.N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2.sup.N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N-1 bit thermometer coded signal.

An analog-to-digital converter (ADC) with split-gate laddered-inverter quantizer is presented herein. The ADC converts, via the split-gate laddered-inverter quantizer, an analog input voltage into a digital output value. The split-gate laddered-inverter quantizer separately couples, during respective phases of a clock signal via respective capacitances, a reference voltage and an input voltage corresponding to the analog input voltage to P-type metal-oxide-semiconductor (PMOS) gates of a PMOS branch of the split-gate laddered-inverter quantizer and N-type metal-oxide-semiconductor (NMOS) gates of an NMOS branch of the split-gate laddered-inverter quantizer to optimize current flow at respective frequencies. Further, the split-gate laddered-inverter quantizer separately biases, during the respective phases of the clock signal, the NMOS gates and the PMOS gates at respective bias voltages to optimize the current flow at the respective frequencies.

A sigma delta modulator device includes a sampling circuit, a digital to analog converter circuit, an integrator circuit, and an analog to digital converter circuit. The sampling circuit is configured to sample an input signal, in order to generate a first signal. The digital to analog converter circuit is configured to convert a first digital signal to be a combination of a first reference voltage and a common mode voltage, in order to generate a second signal, in which the first reference voltage is one of a positive reference voltage and a negative reference voltage. The integrator circuit is configured to perform integration according to the first signal and the second signal, in order to generate a third signal. The analog to digital converter circuit is configured to quantize the third signal to generate an output signal, and to generate the first digital signal according to the output signal.

An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

A digital delta-sigma modulator (DDSM) is disclosed with an input signal x[n], an output signal y[n], a quantization error signal e[n] and a dither signal d[n], having an equation described in the z-domain by

Y(z)=STF(z)X(z)+DTF(z)D(z)−NTF(z)E(z)

wherein Y(z), X(z), D(z) and E(z) are z-transforms of the output signal, the input signal, the dither signal, and the quantization error signal, and wherein STF(z), DTF(z) and NTF(z) correspond to a transfer function of the input signal, a transfer function of the dither signal, and a transfer function of the quantization error signal, and wherein the transfer function of the quantization error signal is of the form:

[00001]$\mathrm{NTF}\left(z\right)={\mathrm{Az}}^{-Q}\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

where A, Q and K are constants, coefficients c.sub.i are real valued and c.sub.K≠0 and wherein at least one of the zeroes z.sub.j of

[00002]$\left(1+\underset{i=1}{\overset{K}{.Math.}}{c}_i{z}^{-i}\right)$

satisfies z.sub.j≠+1 for j=1, 2, . . . , K

A method for virtually performing delta-sigma digitization is provided. The method is performed on a series of digital samples output from a communication stack of a communication network. The method includes steps of obtaining a delta-sigma digitization sampling frequency for the output series of digital samples, calculating an oversampling ratio for the output series of digital samples, interpolating the output series of digital samples at a rate equivalent to the oversampling ratio, and quantizing the interpolated series of digital samples to plurality of discrete predetermined levels.

A digitally-controlled oscillator (DCO) circuit includes a digital-to-analog converter (DAC) to generate a first current based on most significant bits of a multi-bit code received from a time-to-digital converter (TDC) of a digital phase-locked loop (PLL). The DCO circuit further includes a sigma-delta modulator (SDM) to modulate least significant bits of the multi-bit code into a set of digital bits based on a first frequency of a feedback clock of the DPLL. The set of digital bits is to cause the DAC to generate a second current. The DCO circuit further includes a ring oscillator coupled to the DAC, the ring oscillator to generate an alternating-current (AC) output signal having a second frequency corresponding to a combination of the first current and the second current.