A memory controller includes, in one embodiment, a memory interface, a plurality of decoders, and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. Each decoder of the plurality of decoders is configured to determine a bit error rate (BER). The controller circuit configured to generate a plurality of bit-error-rate estimation scan (BES) hypotheses for one wordline of the plurality of wordlines, divide the plurality of BES hypotheses among the plurality of decoders, receive BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjust one or more read locations of the one wordline based on the BER results from the plurality of decoders.

An apparatus is provided for channel encoding in a communication system using an LDPC code. The apparatus includes at least one processor configured to encode input bits using a Bose-Chaudhuri-Hocquenghem (BCH) code, shorten one or more bits of the encoded input bits according to a number of bit groups to be shortened and an order among a plurality of orders according to which the bit groups are shortened, wherein the number of bit groups to be shortened is based on a number of bits to be shortened which is based on a number of the encoded input bits, encode information bits including the encoded input bits and the shortened one or more bits, using an LDPC code to generate parity bits, and puncture one or more bits in the parity bits based on a puncturing parameter among puncturing parameters; and a transmitter configured to transmit a signal that is generated from the encoded information bits based on the punctured one or more bits. The plurality of orders are based on the puncturing parameters and include a first order and a second order that is different from the first order.

The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 17280 bits and the coding rate r of 7/16 or 8/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns. The present technology can be applied to, for example, data transmission using an LDPC code.

Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.

A method includes calculating a number of iterative detection and decoding (IDD) iterations and a number of decoding iterations for each of a plurality of channel coding units in a target codeword; calculating a demodulation time and a decoding time for the target codeword based on the number of IDD iterations and the number of decoding iterations for the target codeword; adding the target codeword to a codeword set, based on a demodulation time and a decoding time for codewords in the codeword set and the target codeword; and performing an IDD operation based on a number of IDD iterations and a number of decoding iterations.

An error rate measuring apparatus includes: an operation unit that sets a codeword length, an FEC symbol length, and an FEC symbol error threshold in accordance with a communication standard of a device under test W; error counting means for counting FEC symbol error detected at one FEC symbol interval and an uncorrectable codeword; a display unit that identifies and displays bit string data according to presence or absence of the FEC symbol error in FEC symbol length units based on a counting result; and display control means for performing display control by setting one zone of a display area of identification display as one FEC symbol length, matching a zone length of a horizontal axis of the display area with one codeword length, and performing line feed in codeword length units.

There is provided a decoding circuit including; a first decoding unit that decodes a first signal from a multiplexed signal in which the first signal and a second signal are multiplexed in an LDM (Layered Division Multiplexing) system; and a second decoding unit that decodes the second signal from the multiplexed signal using the decoding result of the decoded first signal, wherein the second signal is selectively decoded based on noise information related to a reception state of the multiplexed signal.

An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.