A method for forming a thermal oxide film on a semiconductor substrate, including: a correlation acquisition step of providing a plurality of semiconductor substrates; a substrate cleaning step of cleaning a semiconductor substrate; a thermal oxide film thickness estimation step of determining a constitution of a chemical oxide film formed on the semiconductor substrate by the cleaning in the substrate cleaning step and, based on the correlation, estimating a thickness of a thermal oxide film on a hypothesis that the semiconductor substrate has been subjected to a thermal oxidization treatment conditions in the correlation acquisition step; a thermal oxidization treatment condition determination step of determining thermal oxidization treatment conditions based on the thermal oxidization treatment conditions in the correlation acquisition step so that the thermal oxide film is a predetermined thickness; and a thermal oxide film formation step of forming a thermal oxide film on the semiconductor substrate.

Embodiments described herein relate to semiconductor and metal substrate surface preparation and controlled growth methods. An example application is formation of an atomic layer deposition (ALD) control layer as a diffusion barrier or gate dielectric layer and subsequent ALD processing. Embodiments described herein are believed to be advantageously utilized concerning gate oxide deposition, diffusion barrier deposition, surface functionalization, surface passivation, and oxide nucleation, among other processes. More specifically, embodiments described herein provide for silicon nitride ALD processes which functionalize, passivate, and nucleate a SiN.sub.x monolayer at temperatures below about 300° C.

Embodiments of the invention provide self-assembled monolayers (SAM) formulations and cleaning to promote quick depositions. A hydrogen-based plasma clean is performed on a structure, the structure including a metal layer and a dielectric layer. A self-assembled monolayers (SAM) solution is dispensed on the structure, the SAM solution including SAMs and a solvent, the SAMs being configured to assemble on the metal layer. The structure is rinsed with a rinse solution including the solvent.

A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

The present invention concerns a method for forming a metal layer for electromagnetic shielding and thermal management of active components, preferably by wet chemical metal plating, using an adhesion promotion layer on the layer of molding compound and forming at least one metal layer on the adhesion promotion layer or forming at least one metal layer on the adhesion promotion layer by wet chemical metal plating processes.

Various methods for fabricating a semiconductor device by selective in-situ cleaning of a target surface of a semiconductor substrate by selective dry surface atomic layer etching of the target surface film, selectively removing one or more top layers of atoms from the target surface film of the semiconductor substrate. The selective in-situ cleaning of a target surface can be followed by deposition on the cleaned target surface such as to form a cap layer, a conductive contact layer, or a gate dielectric layer.

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Provided is a method of removing native oxide from a substrate, the method including exposing the substrate to trimethyl aluminum (TMA) or dicyclopentadienyl magnesium (MgCp.sub.2) for a predetermined time.

A method for manufacturing a passivation stack on a crystalline silicon solar cell device. The method includes providing a substrate comprising a crystalline silicone layer such as a crystalline silicon wafer or chip, cleaning a surface of the crystalline silicon layer by removing an oxide layer at least from a portion of one side of the crystalline silicon layer, depositing, on at least a part of the cleaned surface, a layer of silicon oxynitride, and depositing a capping layer comprising a hydrogenated dielectric material on top of the layer of silicon oxynitride, wherein the layer of silicon oxynitride is deposited at a temperature from 100° C. to 200° C., and the step of depositing the layer of silicon oxynitride includes using N.sub.2O and SiH.sub.4 as precursor gasses in an N.sub.2 ambient atmosphere and depositing silicon oxynitride with a gas flow ratio of N.sub.2O to SiH.sub.4 below 2.

Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.