A method of forming a memory device that includes forming a sacrificial gate on a surface of a first source/drain region, and forming a channel opening through the sacrificial gate. The method may further include forming an epitaxial channel region is formed in the channel opening that is in situ doped to have an opposite conductivity type as the first of the source/drain region. A second source/drain region is formed on a portion of the epitaxial channel region opposite the portion of the epitaxial channel region that the first source/drain region is present on, wherein the second source/drain region has a same conductivity type as the conductivity type of the first source/drain region. A memory gate structure including a floating gate and a control gate is substituted for the sacrificial gate.

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm.sup.2/Vs to the diamond lattice at 100 kPa and 300K, and wherein the n-type donor atoms are introduced to the lattice through ion tracks.

A semiconductor device and its fabrication method are provided. The method includes providing a base substrate; forming a first well region and a second well region in the base substrate; forming a gate electrode structure, sidewall spacers, a doped source layer, a doped drain layer and a dielectric layer over the base substrate, where the doped source layer and the doped drain layer are respectively on two sides of the gate electrode structure and the sidewall spacers, and the gate electrode structure and the sidewall spacers are over the first well region and the second well region; removing a portion of the gate electrode structure on the second well region and a portion of the base substrate of the second well region to form a trench in the dielectric layer, where the trench exposes a portion of the sidewall spacers; and forming an isolation layer in the trench.

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm.sup.2/Vs to the diamond lattice at 100 kPa and 300K, and Wherein the n-type donor atoms are introduced to the lattice through ion tracks.

The present invention addresses the problem of providing a novel SiC epitaxial substrate manufacturing method and manufacturing device therefor. An SiC substrate and an SiC material, which has a lower doping concentration than said SiC substrate, are heated facing one another, and material is transported from the SiC material to the SiC substrate to form an SiC epitaxial layer. As a result, in comparison with the existing method (chemical vapour deposition), it is possible to provide an SiC epitaxial substrate manufacturing method with a reduced number of parameters to be controlled.

The present disclosure relates to a strategy to synthesize antimony- and zinc-doped tin oxide particles with tunable band gap characteristics. The methods yield stable and monodispersed particles with great control on uniformity of shape and size. The methods produce undoped and antimony and zinc-doped tin oxide stand-alone and core-shell particles, both nanoparticles and microparticles, as well as antimony and zinc-doped tin oxide shells for coating particles, including plasmonic core particles.

A method of manipulating deposition rates of poly-silicon and a method of manufacturing a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device are provided. The method of manipulating deposition rates of poly-silicon includes: providing a substrate, where a first surface of the substrate includes at least two of an oxide material region, a silicon nitride material region and a silicon material region; performing a first treatment on the first surface of the substrate, so as to manipulate the deposition rates of poly-silicon on different regions of the first surface to be closer; and forming a poly-silicon layer on the first surface of the substrate.

A method for producing a doping raw-material solution for film formation includes a step of firstly mixing a solute including a halogen-containing organic dopant compound or a dopant halide with a first solvent, but not with other solvents to prepare a dopant precursor solution separately from a film-forming raw material, where an acidic solvent is used as the first solvent. A method for producing a doping raw-material solution for film formation enables stable formation of a high-quality thin film having excellent electric characteristics.

The present invention is directed to a method as well as to a machine for producing a starting material for a silicon solar cell with passivated contacts.

A semiconductor device is provided. The semiconductor device includes a base substrate; a first well region and a second well region in the base substrate; a gate electrode structure, sidewall spacers, a doped source layer and a doped drain layer over the base substrate; a dielectric layer on the base substrate; and an isolation layer in the dielectric layer. The dielectric layer covers sidewalls of the sidewall spacers, the doped source layer and the doped drain layer, and exposes a top surface of the gate electrode structure. The isolation layer is in the gate electrode structure of the second well region and the base substrate of the second well region, and adjacent to the sidewalls of the sidewall spacer over the second well region.