A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.

A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.

A wafer processing method for processing a wafer formed on a front surface thereof with a plurality of devices having projection-shaped electrodes, the devices being partitioned by streets, includes a cutting step of holding a back surface of the wafer by a holding surface of a chuck table and cutting head portions of the projection-shaped electrodes by a cutting tool slewed in parallel to the holding surface, to make uniform the electrodes in height and expose metallic surfaces; a thermocompression bonding sheet laying step of laying a thermocompression bonding sheet on the front surface of the wafer; a thermocompression bonding step of heating and pressing the thermocompression bonding sheet to perform thermocompression bonding; and a peeling step of peeling off the thermocompression bonding sheet from the wafer, before dividing the wafer into individual device chips and bonding the electrodes to a circuit board.

The present invention relates to a polishing apparatus and a polishing method for polishing a workpiece, such as a wafer on which a pattern is formed, on a polishing pad, and more particularly, relates to a polishing apparatus and a polishing method for detecting a geometric element of a pattern, such as a pitch. The polishing apparatus includes: a polishing table (3) configured to support a polishing pad (2); a polishing head (1) configured to press a workpiece (W), having a pattern formed therein, against the polishing pad (2) and polish a surface of the workpiece (W), an imaging device (20) disposed in the polishing table (3) and configured to generate an image including at least the pattern of the workpiece (W), and an image analysis system (30) configured determining a geometric element of the pattern of the workpiece (W) based on the image.

A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

Methods and apparatus reduce chucking abnormalities for electrostatic chucks by ensuring proper planarizing of ceramic surfaces of the electrostatic chuck. In some embodiments, a method for planarizing an upper ceramic surface of an electrostatic chuck assembly may comprise placing the electrostatic chuck assembly in a first planarizing apparatus, altering an upper ceramic surface of the electrostatic chuck assembly, and halting the altering of the upper ceramic surface of the electrostatic chuck assembly when an S.sub.a parameter is less than approximately 0.1 microns, an S.sub.dr parameter is less than approximately 2.5 percent, an S.sub.z parameter is less than approximately 10 microns for any given area of approximately 10 mm.sup.2 of the upper ceramic surface, or a pit-porosity depth parameter of greater than 1 micron is less than approximately 0.1 percent of area of the upper ceramic surface.

Methods and apparatus reduce chucking abnormalities for electrostatic chucks by ensuring proper planarizing of ceramic surfaces of the electrostatic chuck. In some embodiments, a method for planarizing an upper ceramic surface of an electrostatic chuck assembly may comprise placing the electrostatic chuck assembly in a first planarizing apparatus, altering an upper ceramic surface of the electrostatic chuck assembly, and halting the altering of the upper ceramic surface of the electrostatic chuck assembly when an S.sub.a parameter is less than approximately 0.1 microns, an S.sub.dr parameter is less than approximately 2.5 percent, an S.sub.z parameter is less than approximately 10 microns for any given area of approximately 10 mm.sup.2 of the upper ceramic surface, or a pit-porosity depth parameter of greater than 1 micron is less than approximately 0.1 percent of area of the upper ceramic surface.

The present description concerns an electronic die manufacturing method comprising: a) the deposition of an electrically-insulating resin layer on the side of a first surface of a semiconductor substrate, inside and on top of which have been previously formed a plurality of integrated circuits, the semiconductor substrate supporting on a second surface, opposite to the first surface, contacting pads; and b) the forming, on the side of the second surface of the semiconductor substrate, of first trenches, electrically separating the integrated circuits from one another, the first trenches vertically extending in the semiconductor substrate and emerging into or on top of the resin layer.

Disclosed is a chemical mechanical polishing solution containing cerium oxide, polyacrylic acid, polyether amine and water. In this invention polyether amine can serve as an additive to reduce the dishing amount of patterned wafer by negatively charged cerium oxide, and improve the efficiency of planarization.