The invention provides a method for polishing or planarizing a substrate of at least one of semiconductor, optical and magnetic substrates. The method includes attaching a polymer-polymer composite polishing pad having a polishing layer to a polishing device. A hydrophilic polymeric matrix forms the polishing layer. Cationic fluoropolymer particles having nitrogen-containing end groups are embedded in the polymeric matrix. A slurry containing anionic particles is applied to the polymer-polymer composite polishing pad and rubbed against the substrate to polish or planarize the substrate with the fluoropolymer particles interacting with the anionic particles to increase polishing removal rate.

Disclosed are methods of fabricating semiconductor devices and methods of separating substrates. The semiconductor device fabricating method comprises providing a release layer between a carrier substrate and a first surface of a device substrate to attach the device substrate to the carrier substrate, irradiating the carrier substrate with an ultraviolet ray to separate the carrier substrate from the release layer and to expose one surface of the release layer, and performing a cleaning process on the one surface of the release layer to expose the first surface of the device substrate. The release layer includes an aromatic polymerization unit and a siloxane polymerization unit.

The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes a support unit horizontally maintaining a substrate; a laser irradiation unit for irradiating the substrate with a laser; a photo-detector for detecting an energy of a reflective light reflected from the substrate among a laser irradiated on the substrate; and a processor, and wherein the processor irradiates a first laser of a first output to the substrate, and sets a second output of a second laser for irradiating the substrate to heat the substrate, based on an energy of a first reflective light reflected from the substrate by the first laser detected from the photo-detector.

A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.

A method used in forming an array of memory cells comprises forming lines of top-source/drain-region material, bottom-source/drain-region material, and channel-region material vertically there-between in rows in a first direction. The lines are spaced from one another in a second direction. The top-source/drain-region material, bottom-source/drain-region material, and channel-region material have respective opposing sides. The channel-region material on its opposing sides is laterally recessed in the second direction relative to the top-source/drain-region material and the bottom-source/drain-region material on their opposing sides to form a pair of lateral recesses in the opposing sides of the channel-region material in individual of the rows. After the pair of lateral recesses are formed, the lines of the top-source/drain-region material, the channel-region material, and the bottom-source/drain-region material are patterned in the second direction to comprise pillars of individual transistors. Rows of wordlines are formed in the first direction that individually are operatively aside the channel-region material of individual of the pillars in the pairs of lateral recesses and that interconnect the transistors in that individual row. Other embodiments, including structure independent of method, are disclosed.

Methods and apparatuses for selective monitoring of multiple silicon compounds in etchant solutions are provided. Methods can include reacting a test solution comprising a plurality of different silicon compounds with a fluoride-based compound in several conditions to provide different silicon:reagent binding ratios. One of the conditions can include the addition of a co-solvent to the test solution. Concentrations of the multiple silicon compounds can be determined based on the different binding ratios of silicon:reagent. Methods can further include a measuring method such as silicon elemental analysis or measuring of functional groups of a certain silicon form of a first portion of a test solution comprising a plurality of different silicon compounds and reacting a second portion of the solution with a fluoride-based compound to provide a silicon:reagent binding ratio. Concentrations of the multiple silicon compounds can be determined based on the measuring method and binding ratio measurements.

The present invention relates to an etching composition for selectively etching a silicon nitride layer. The etching composition includes an inorganic acid, an epoxy-based silicon compound, and water. The etching composition of the present invention selectively removes a silicon nitride layer while minimizing damage to an underlying metal layer and preventing a silicon oxide layer from being etched.

A method is provided for forming at least one trench to be filled with an isolating material to form an isolating trench, in a substrate based on a semiconductor material, the method including at least the following successive steps: providing a stack including at least the substrate, a first hard mask layer, and a second hard mask layer; making at least a first opening and a second opening, by carrying out isotropic etchings; performing a third, anisotropic, etching of the substrate in line with the second opening, so as to obtain the at least one trench; performing a fourth, isotropic, etching of the first layer so as to enlarge the first opening and obtain a first enlarged opening; and performing a fifth, anisotropic, etching so as to simultaneously enlarge the second opening and increase a depth of the at least one trench.

A method for etching a main surface of a thin layer of a substrate, which comprises immersing the substrate n an etching bath so as to expose the main surface to an etching agent, the substrate being oriented relative to the bath such that: —when it is introduced into the bath, the main surface is gradually immersed from an initial introduction point (PII) to an end introduction point (PFI), at an introduction speed, and —when it exits the bath, the main surface gradually emerges from an initial exit point (PIS) to an end exit point (PFS), at an exit speed, the method being characterized in that: —the introduction speed is chosen in such a way as to etch the main surface according to a first non-uniform profile between the initial introduction point (PII) and the end introduction point (PFI), and/or —the exit speed is chosen in such a way as to etch the main surface according to a second non-uniform profile between the initial exit point (PIS) and the end exit point (PFS), in order to compensate for non-uniformities in the thickness of the thin layer.

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.