A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

The present disclosure provides a semiconductor device structure with conductive contact of different widths and a method for preparing the semiconductor device structure. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate, and a first conductive contact penetrating through the dielectric layer. The first conductive contact includes a first metal filling layer and a first metal silicide structure surrounding the first metal filling layer. The semiconductor device structure also includes a second conductive contact penetrating through the dielectric layer. The second conductive contact includes a second metal filling layer and a second metal silicide structure surrounding the second metal filling layer, and a first width of the first conductive contact is different from a second width of the second conductive contact.

A small-sized and highly functional imaging device is provided. The imaging device includes a photoelectric conversion device formed on a silicon substrate and a transistor including a channel formation region in a silicon epitaxial growth layer formed on the silicon substrate. The transistor provided in the epitaxial growth layer has favorable electrical characteristics, so that the imaging device with little noise can be formed. Since the transistor can be formed so as to have a region overlapping with the photoelectric conversion device, the imaging device can be downsized.

A selective liquid sliding surface includes: a base layer; multiple pillars protruding from the base layer; and a head protruding from an upper surface of each of the multiple pillars and having a larger cross-sectional diameter than the pillar, wherein the head includes a first head protruding from the pillar and a second head protruding from a periphery of the first head, and the base layer, the pillar, and the head are formed of the same material.

Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. Interfacial properties of AMMFs are superior to those of crystalline metal films, and therefore electric fields at the interface of an AMMF and an oxide film are more uniform. An AMMF resistor (AMNR) can be constructed as a three-layer structure including an amorphous metal, a tunneling insulator, and a crystalline metal layer. By modifying the order of the materials, the patterns of the electrodes, and the size and number of overlap areas, the I-V performance characteristics of the AMNR are adjusted. A non-coplanar AMNR has a five-layer structure that includes three metal layers separated by metal oxide tunneling insulator layers, wherein an amorphous metal thin film material is used to fabricate the middle electrodes.

Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. Interfacial properties of AMMFs are superior to those of crystalline metal films, and therefore electric fields at the interface of an AMMF and an oxide film are more uniform. An AMMF resistor (AMNR) can be constructed as a three-layer structure including an amorphous metal, a tunneling insulator, and a crystalline metal layer. By modifying the order of the materials, the patterns of the electrodes, and the size and number of overlap areas, the I-V performance characteristics of the AMNR are adjusted. A non-coplanar AMNR has a five-layer structure that includes three metal layers separated by metal oxide tunneling insulator layers, wherein an amorphous metal thin film material is used to fabricate the middle electrodes.

The degree of freedom of an abnormality detection target location in a solid-state imaging device in which a plurality of substrates are joined is improved. A semiconductor device includes a connection line and a detection circuit. A plurality of semiconductor substrates are joined in the semiconductor device. Then, in the semiconductor device, the connection line is wired across the plurality of semiconductor substrates. The detection circuit detects the presence or absence of an abnormality in a joint surface of the plurality of semiconductor substrates based on an energization state of the connection line when enable has been set by a predetermined control signal.

A substrate processing method includes: a carry-in step of carrying a substrate having a silicon-containing film on a surface of the substrate into a processing container; a first step of forming an adsorption layer by supplying an oxygen-containing gas into the processing container and causing the oxygen-containing gas to be adsorbed on a surface of the silicon-containing film; a second step of forming a silicon oxide layer by supplying an argon-containing gas into the processing container and causing the adsorption layer and the surface of the silicon-containing film to react with each other with plasma of the argon-containing gas; and a third step of forming a graphene film on the silicon oxide layer by supplying a carbon-containing gas into the processing container with plasma of the carbon-containing gas.

A packaged integrated circuit includes a core structure with a cavity therein; a component accommodated in the cavity; an electrically insulating structure formed over the core structure and the component; a partially electrically insulating carrier structure formed below the core structure and the component; and an electrically conducting redistribution arrangement formed at least partially within the carrier structure. The redistribution arrangement includes conductor structures each having a first element extending through the carrier structure and electrically connecting a contact of the component and a second element below the carrier structure. A part of the second element is a contact pad for electrically connecting the redistribution arrangement with external circuitry. The carrier structure includes a polyimide layer and an adhesive layer. The adhesive layer is directly attached to an upper surface of the polyimide layer and to a lower surface of the core structure and a lower surface of the component.