A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

There is provided a method for manufacturing a nitride semiconductor template constituted by forming a nitride semiconductor layer on a substrate, comprising: (a) preparing a pattern-substrate as the substrate, with a concavo-convex pattern formed on a front surface of the pattern-substrate, (b) forming a first layer by epitaxially growing a nitride semiconductor containing aluminum on the concavo-convex pattern of the pattern-substrate, in a thickness of not flattening a front surface; (c) applying annealing to the first layer; and (d) forming a second layer by epitaxially growing a nitride semiconductor containing aluminum so as to overlap on the first layer after performing (c), and in a thickness of flattening a front surface, and constituting the nitride semiconductor layer by the first layer and the second layer.

A method for treating a substrate includes receiving the substrate in a vacuum process chamber. The substrate includes a III-V film layer disposed on the substrate. The III-V film layer includes an exposed surface, an interior portion underlying the exposed surface, and one or more of the following: Al, Ga, In, N, P, As, Sb, Si, or Ge. The method further includes altering the chemical composition of the exposed surface and a fraction of the interior portion of the III-V film layer to form an altered portion of the III-V film layer using a first plasma treatment, removing the altered portion of the III-V film layer using a second plasma treatment, and repeating the altering and removing of the III-V film layer until a predetermined amount of the III-V film layer is removed from the substrate.

Methods are provided of selectively obtaining n-type and p-type regions from the same III-Nitride layer deposited on a substrate without using diffusion or ion-implantation techniques. The III-Nitride layer is co-doped simultaneously with n-type and p-type dopants, with p-type dopant concentration higher than n-type dopant to generate p-n junctions. The methods rely on obtaining activated p-type dopants only in selected regions to generate p-type layers, whereas the rest of the regions effectively behave as an n-type layer by having deactivated p-type dopant atoms.

A semiconductor manufacturing method includes a metal thin film deposition step of depositing a metal thin film on a donor or acceptor-doped nitride semiconductor, and a laser beam irradiation step of irradiating the deposited metal thin film with a laser beam.

A p-n diode includes a first electrode, a n-GaN layer on the first electrode, a p-GaN layer on the n-GaN layer, and a second electrode on a first portion of the p-GaN layer. A region of the p-GaN layer surrounding the electrode is a passivated region. Treating a GaN power device having a p-GaN layer includes covering a portion of the p-GaN layer with a metal layer, exposing the p-GaN layer to a hydrogen plasma, and thermally annealing the p-GaN layer, thereby passivating a region of the p-GaN layer proximate the metal layer.

A conductive, porous gallium-nitride layer can be formed as an active layer in a multilayer structure adjacent to one or more p-type III-nitride layers, which may be buried in a multilayer stack of an integrated device. During an annealing process, dopant-bound atomic species in the p-type layers that might otherwise neutralize the dopants may dissociate and out-diffuse from the device through the porous layer. The release and removal of the neutralizing species may reduce layer resistance and improve device performance.

Systems and methods of the disclosed embodiments include reducing defects in a semiconductor layer. The defects may be reduced by forming the semiconductor layer on a substrate, removing at least a portion the substrate from an underside of the semiconductor layer, and annealing the semiconductor layer to reduce the defects in the layer. The annealing includes focusing energy at the layer.

Methods for activating a p-type dopant in a group III-Nitride semiconductor are provided. In embodiments, such a method comprises annealing, in situ, a film of a group III-Nitride semiconductor comprising a p-type dopant formed via metalorganic chemical vapor deposition (MOCVD) at a first temperature for a first period of time under an atmosphere comprising NH.sub.3 and N.sub.2; and cooling, in situ, the film of the group III-Nitride semiconductor to a second temperature that is lower than the first temperature under an atmosphere comprising N.sub.2 in the absence of NH.sub.3, to form an activated p-type group III-Nitride semiconductor film.

Systems and methods of the disclosed embodiments include reducing defects in a semiconductor layer. The defects may be reduced by forming the semiconductor layer on a substrate, removing at least a portion the substrate from an underside of the semiconductor layer, and annealing the semiconductor layer to reduce the defects in the layer. The annealing includes focusing energy at the layer.