Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 10.sup.18-10.sup.22 cm.sup.−3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N.sub.2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).

A p-n diode includes a first electrode, a n-GaN layer on the first electrode, a p-GaN layer on the n-GaN layer, and a second electrode on a first portion of the p-GaN layer. A region of the p-GaN layer surrounding the electrode is a passivated region. Treating a GaN power device having a p-GaN layer includes covering a portion of the p-GaN layer with a metal layer, exposing the p-GaN layer to a hydrogen plasma, and thermally annealing the p-GaN layer, thereby passivating a region of the p-GaN layer proximate the metal layer.

A method includes depositing a first epitaxial layer of an aluminum gallium nitride (AlGaN) material onto a preliminary substrate and polishing the first layer's surface. Ions are implanted beneath the surface, which is bonded to a seed insulating substrate. Annealing is performed, resulting in second epitaxial layer on preliminary substrate and third epitaxial layer on seed insulating substrate. Third layer's surface is polished to obtain a seed wafer. In some implementations, a fourth epitaxial layer of a second AlGaN material is deposited onto surface of third layer. Fourth layer's surface is polished, and ions are implanted beneath the surface, which is bonded to a product insulating substrate. Annealing is performed, resulting in fifth epitaxial layer on seed insulating substrate and sixth epitaxial layer on product insulating substrate. The sixth layer can be used to obtain an AlGaN product, and the fifth layer can be reused to fabricate additional AlGaN products.

A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A surface of the p-type region perpendicular to a growth direction of the semiconductor structure includes a first portion and a second portion. The first portion is less conductive than the second portion. The device further includes a p-contact formed on the p-type region. The p-contact includes a reflector and a blocking material. The blocking material is disposed over the first portion and no blocking material is disposed over the second portion.

The present invention relates to technology for fabricating a gallium nitride substrate using an ion implantation process to which a self-separation technique is applied. According to the present invention, a method of fabricating a gallium nitride substrate may include a step of forming a first gallium nitride layer on a substrate, a step of implanting hydrogen ions into the first gallium nitride layer to form a separation layer, a step of grinding the edges of the substrate, the first gallium nitride layer, and the separation layer, a step of forming a second gallium nitride layer on the first gallium nitride layer having a ground edge, and a step of self-separating the second gallium nitride layer from the first gallium nitride layer having a ground edge.

Provided is a technology for obtaining a drain current of a sufficient magnitude in a field effect transistor using a nitride semiconductor. A channel layer that is Al.sub.x1In.sub.y1Ga.sub.1-x1-y1N is formed on an upper surface of a semiconductor substrate, and on an upper surface of the channel layer, a barrier layer that is Al.sub.x2In.sub.y2Ga.sub.1-x2-y2N having a band gap larger than that of the channel layer is formed. Then, on an upper surface of the barrier layer, a gate insulating film that is an insulator or a semiconductor and has a band gap larger than that of the barrier layer is at least partially formed, and a gate electrode is formed on an upper surface of the gate insulating film. Then, heat treatment is performed while a positive voltage is applied to the gate electrode.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a first insulating layer. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Al.sub.x1Ga.sub.1-x1N and includes a first partial region, a second partial region, and a third partial region. The second semiconductor layer includes Al.sub.x2Ga.sub.1-x2N. A portion of the second semiconductor layer is between the third partial region and the third electrode in the second direction. The first insulating layer includes a first insulating region. The first insulating region is between the third electrode and the portion of the second semiconductor layer in the second direction.

According to the preparation method for a semiconductor structure provided in the present application, a selective epitaxial growth method is used, without etching the n-type semiconductor layer and the p-type semiconductor layer, thus avoiding problems such as uncontrollable etching depth and damaged etched surface, which effectively reduces gate leakage, maintains low resistance in a channel region, suppresses current collapse, and improves reliability and stability of a device.

A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 10.sup.18-10.sup.22 cm.sup.−3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N.sub.2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).