A method for forming a semiconductor structure includes: a substrate is provided, in which active areas arranged in a matrix and isolation structures for isolating active areas from each other are formed in substrate, a first direction is a column direction of matrix and a second direction is a row direction of matrix; a conductive layer is formed on substrate; at least conductive layer is etched to form a plurality of bit line grooves extending along first direction and arranged along second direction and a plurality of conductive lines extending along first direction and arranged along second direction; a bit line structure is formed in each bit line groove, in which a gap is formed between bit line structure and each of two sides of a respective one of bit line grooves; and conductive lines are etched along second direction to form conductive pillars serving as storage node contact structures.

Provided is a method for manufacturing a semiconductor silicon wafer capable of inhibiting P-aggregation defects (Si-P defects) and SF in an epitaxial layer. The method includes a step of forming a silicon oxide film with a thickness of at least 300 nm or thicker only on the backside of the silicon wafer substrate by the CVD method at a temperature of 500° C. or lower after the step of forming the silicon oxide film, a step of heat treatment where the substrate is kept in an oxidizing atmosphere at a constant temperature of 1100° C. or higher and 1250° C. or lower for 30 minutes or longer and 120 minutes or shorter after the heat treatment, a step of removing surface oxide film formed on the front surface of the substrate, and a step of depositing a silicon monocrystalline epitaxial layer on the substrate after the step of removing the surface oxide film.

A substrate treatment apparatus according to an embodiment includes a treatment tank to store a chemical solution to treat a substrate, a pipe having a discharge port through which an air bubble is discharged from a bottom of the treatment tank toward the substrate, and a rod body disposed between the discharge port and the substrate to divide the air bubble.

A wafer surface treatment device and a method thereof are disclosed. The wafer surface treatment device includes a main body internally defining a treatment space; a movable door provided on one side of the main body; a gas atomizer provided in the treatment space; a heater provided in the treatment space; and a control unit connected to the gas atomizer and the heater.

A method for analyzing a semiconductor device includes repeatedly etching an entire surface of a wafer at a same etch rate by a target depth to expose a next surface of the wafer. The method includes obtaining two-dimensional structure information from each repeatedly etched surface of the wafer and serially stacking the repeatedly obtained two-dimensional structure information to generate a three-dimensional image.

A wafer cleaning apparatus is provided. The wafer cleaning apparatus includes comprising a chamber configured to be loaded with a wafer, a nozzle on the wafer and configured to provide liquid chemicals on an upper surface of the wafer, a housing under the wafer, a laser module configured to irradiate laser on the wafer, a transparent window disposed between the wafer and the laser module, and a controller configured to control on/off of the laser module, wherein the controller is configured to control repetition of turning the laser module on and off, and retain temperature of the wafer within a temperature range, and a ratio of time when the laser module is on in one cycle including on/off of the laser module is 30% to 50%.

Examples are disclosed that relate to planarizing substrates without use of an abrasive. One example provides a method of chemically planarizing a substrate, the method comprising introducing an abrasive-free planarization solution onto a porous pad, contacting the substrate with the porous pad while moving the porous pad and substrate relative to one another such that higher portions of the substrate contact the porous pad and lower portions of the substrate do not contact the porous pad, and removing material from the higher portions of the substrate via contact with the porous pad to reduce a height of the higher portions of the substrate relative to the lower portions of the substrate.

A manufacturing process of wafer thinning includes a step of wafer-grinding to grind a surface of a wafer to a first predetermined thickness, and a step of wafer-etching to etch the grinded face of the wafer with the first predetermined thickness to a second predetermined thickness.

An apparatus for chemical mechanical polishing includes a rotatable platen having a surface to support a polishing pad, a carrier head to hold a substrate in contact with the polishing pad, and a polishing liquid distribution system. The polishing liquid distribution system includes a dispenser positioned to deliver a polishing liquid to a portion of a polishing surface of the polishing pad, and a first barrier positioned before the portion of the polishing surface and configured to block used polishing liquid from reaching the portion of the polishing surface. The first barrier includes a solid first body having a first flat bottom surface and having a first leading surface configured to contact the used polishing liquid.

A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region.