A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the first source/drain region comprises a smaller cross-section than the second source/drain region, a first dielectric material disposed in contact with a bottom surface and vertical surfaces of the first source/drain region and further in contact with a vertical surface and top surface of the second source/drain region, and a second dielectric material disposed as an interlayer dielectric material encapsulating the first and second transistors.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.

A device area and a marking area neighboring the device area over a dielectric stack are determined. The dielectric stack includes insulating material layers and sacrificial material layers arranged alternatingly over a substrate. The device area and the marking area are patterned using a same etching process to form a marking pattern having a central marking structure in a marking area and a staircase pattern in the device area. The marking pattern and the staircase pattern have a same thickness equal to a thickness of at least one insulating material layer and one sacrificial material layer, and the central marking structure divides the marking area into a first marking sub-area farther from the device area and a second marking sub-area closer to the device area. A first pattern density of the first marking sub-area is greater than or equal to a second pattern density of the second marking sub-area. A photoresist layer is formed to cover the staircase pattern and expose the marking pattern, and the photoresist layer is trimmed to expose a portion of the dielectric stack along a horizontal direction. An etching process is performed to maintain the marking pattern and remove the exposed portion of the dielectric stack and form a staircase.

A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;

a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.

A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of a interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.

Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

Techniques regarding anchors for fins comprised within stacked VTFET devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a fin extending from a semiconductor body. The fin can be comprised within a stacked vertical transport field effect transistor device. The apparatus can also comprise a dielectric anchor extending from the semiconductor body and adjacent to the fin. Further, the dielectric anchor can be coupled to the fin.

An example includes a semiconductor structure including a semiconductor layer, front-side logic devices arranged in a front-side of the semiconductor layer, four epitaxial layers on a back-side of the semiconductor layer, where the four epitaxial layers include a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type, a third epitaxial layer of the second conductivity type, and a fourth epitaxial layer of the first conductivity type, a plurality of back-side contacts exposed at a back-side surface of the fourth epitaxial layer, where the plurality of back-side contacts include a set of first terminal contacts extending into and contacting the fourth epitaxial layer, a set of second terminal contacts extending into and contacting the second epitaxial layer, a set of first gate contacts extending into the third epitaxial layer, and a set of second gate contacts extending into the first epitaxial layer.

A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.