A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.

An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants are blocked from the logic MOS transistors.

A method of forming a Bipolar Junction Transistor (BJT) includes forming an elongated collector line, forming an elongated emitter line parallel to the collector line, and forming an elongated base line parallel to the collector line and positioned between the collector line and the base line. The emitter line, the base line, and the collector line are formed over fin structures.

A combined isolator and power switch is disclosed. Such devices are useful in isolating low voltage components such as control compilers from motors or generators working at high voltages. The combined isolator and power switch includes circuits to transfer internal power from its low voltage side to the switch driver circuits on the high voltage side. The combined isolator and switch is compact and easy to use.

An integrated electronic detector operates to detecting a variation in potential on an input terminal. The detector includes a MOS transistor having a drain forming an output. Variation in drain current is representative of the variation in potential. A bipolar transistor has a base forming the input terminal and a collector electrically connected to the gate of the MOS transistor. The detector has a first configuration in which the bipolar transistor is conducting and the MOS transistor is turned off. The detector has a second configuration in which the bipolar transistor is turned off and the MOS transistor is in a sub-threshold operation. Transition of the detector from the first configuration to the second configuration occurs in response to the variation in potential.

A semiconductor device is provided that includes a composite semiconductor body including a high voltage depletion-mode transistor and a low voltage enhancement-mode transistor. The high voltage depletion-mode transistor is stacked on the low voltage enhancement-mode transistor so that an interface is formed between the high voltage depletion-mode transistor and the low voltage enhancement-mode transistor. The low voltage enhancement-mode transistor includes a current path coupled in series with a current path of the high voltage depletion-mode transistor, and a control electrode is arranged at the interface.

One illustrative method disclosed includes forming an isolation structure so as to define first and second active regions on the SOI substrate, forming a field effect transistor above the first active region and forming an opening in the second active region that exposes an upper surface of the bulk semiconductor layer in the second active region. In this example, the method further includes performing a common epitaxial growth process so as to form an epi semiconductor material region above each of the source/drain regions of the transistor and to form a unitary epi semiconductor structure above the second active region, wherein the unitary epi semiconductor structure is formed on and in contact with the exposed upper surface of the bulk semiconductor layer within the opening and on and in contact with an upper surface of the active layer in the second active region.

Semiconductor component comprising at least two semiconductor regions are disclosed. In one embodiment the semiconductor regions of the semiconductor component are electrically isolated from one another by an insulator, and a deposited, patterned, metallic layer extends over the semiconductor regions and over the insulator.

An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.

After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.