The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

A resistive element includes: a semiconductor substrate; a lower insulating film deposited on the semiconductor substrate; a resistive layer deposited on the lower insulating film; an interlayer insulating film covering the resistive layer; a pad-forming electrode deposited on the interlayer insulating film, and including a first edge portion connected to one edge portion of the resistive layer and a second edge portion opposite to the first edge portion to be in electrical Schottky contact with the semiconductor substrate; a relay wire having one edge connected to another edge portion of the resistive layer to form an ohmic contact to the semiconductor substrate; and a counter electrode provided under the semiconductor substrate, wherein the resistive element uses a resistance value between the pad-forming electrode and the counter electrode.

A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.

The present application provides methods for manufacturing BiCMOS device and the heterojunction bipolar transistor (HBT) contained therein. In formation of a raised extrinsic base region of the heterojunction bipolar transistor, the epitaxial silicon is doped with carbon (C) and boron (B) in situ and is doped with a metal catalyst simultaneously, then, the plasma treatment and the laser annealing are conducted to the carbon, and a graphene region is formed in the Si epitaxial layer. Because of high conductivity of graphene, the base resistance of the SiGe HBT can be reduced to enhance its radiation performance. The above method can be applied to conventional BiCMOS device process by performing plasma treatment and laser annealing to the doped carbon to form the graphene region in the extrinsic base region. The method is easily controlled and integrated into conventional BiCMOS device process.

A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a first conductor and a second insulator over a first insulator; a third insulator over the first conductor and the second insulator; a fourth insulator over the third insulator; a first oxide over the fourth insulator; a second oxide and a third oxide over the first oxide; a second conductor in contact with a top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the second oxide, and a top surface of the second oxide; a third conductor in contact with the top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the third oxide, and a top surface of the third oxide; a fourth oxide over the first oxide; a fifth insulator over the fourth oxide; and a fourth conductor over the fifth insulator. The capacitor includes a fifth conductor over the first insulator, the third insulator over the fifth conductor, and the second conductor over the third insulator.

An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and electrically isolated from the transistor.

An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

A modeling circuit of a field effect transistor includes a first field effect transistor, a first bipolar transistor, a second bipolar transistor and a substrate resistor. The first bipolar transistor has a collector electrode connected to a first node corresponding to a first electrode of the first field effect transistor, an emitter electrode connected to a second node corresponding to a second electrode of the first field effect transistor, and a base electrode. The second bipolar transistor has a collector electrode connected to the second node, an emitter electrode connected to the first node, and a base electrode connected to the base electrode of the first bipolar transistor. The substrate resistor is connected between the base electrodes of the first and second bipolar transistors and a first surface of a semiconductor substrate on which the first field effect transistor is formed.

A semiconductor device structure and method for manufacturing the same are provided. The method includes forming a first resistive element over a substrate, and the first resistive element has a first sidewall extending in a first direction and a second sidewall opposite to the first sidewall and extending in the first direction. The method further includes forming a first conductive feature and a second conductive feature over and electrically connected to the first resistive element and forming a second resistive element over the first resistive element and spaced apart from the first resistive element in a second direction. In addition, the second resistive element is located between the first sidewall and the second sidewall of the first resistive element in a top view, and the first resistive element and the second resistive element are made of different nitrogen-containing materials.

A semiconductor device, allowing easy hole extraction, including a semiconductor substrate having drift and base regions; and transistor and diode portions, in which trench portions and mesa portions are formed, is provided. The transistor portion includes emitter and contact regions above the base region and exposed to an upper surface of the semiconductor substrate. The emitter region has a higher concentration than the drift region. The contact region has a higher concentration than the base region. The mesa portions include boundary mesa portion(s) at a boundary between the transistor and diode portions. The trench portions include dummy trench portion(s) provided adjacent to a trench portion adjacent to the boundary mesa portion(s) and provided on the transistor portion side relative to the trench portion adjacent to the boundary mesa portion(s). The boundary mesa portion(s) include a base boundary mesa portion in which the base region is exposed to the upper surface.