A circuit includes a first bipolar junction transistor (BJT) including a first base, a first collector, and a first emitter, the first collector connected to a first supply voltage node and a second BJT including a second base, a second collector, and a second emitter, the second collector connected to the first emitter at an output node. The circuit also includes a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node. A current source device is also included that is connected in parallel with the capacitor.

E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.

A semiconductor device includes an IGBT as a switching element, and a diode. The IGBT includes: a p type channel doped layer formed in a surface layer part on a front side of a semiconductor substrate; a p.sup.+ type diffusion layer and an n.sup.+ type source layer individually selectively formed in a surface layer part of the p type channel doped layer; and an emitter electrode connected to the n.sup.+ type source layer and the p.sup.+ type diffusion layer. A part of the p type channel doped layer reaches a front-side surface of the semiconductor substrate and is connected to the emitter electrode. On the front-side surface of the semiconductor substrate, the p.sup.+ type diffusion layer is interposed between the p type channel doped layer and an n.sup.+ type source layer, and the p type channel doped layer and the n.sup.+ type source layer are not adjacent to each other.

A semiconductor device includes the following elements. A chip has a main surface substantially parallel with a plane defined by first and second directions intersecting with each other. A power amplifier amplifies an input signal and outputs an amplified signal from plural output terminals. First and second filter circuits attenuate harmonics of the amplified signal. The first filter circuit includes a first capacitor connected between the plural output terminals and a ground. The second filter circuit includes a second capacitor connected between the plural output terminals and a ground. On the main surface of the chip, the plural output terminals are disposed side by side in the first direction, and the first capacitor is disposed on a side in the first direction with respect to the plural output terminals, while the second capacitor is disposed on a side opposite the first direction with respect to the plural output terminals.

A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.

Provided is a semiconductor device comprising: a semiconductor substrate; an active section provided in the semiconductor substrate; an edge termination structure section provided between the active section and an outer peripheral edge of the semiconductor substrate on an upper surface of the semiconductor substrate; and an end lifetime control unit that is provided in the semiconductor substrate in the edge termination structure section and is continuous in a range facing at least two or more diode sections arranged in the first direction, wherein the active section includes: a transistor section and the diode sections alternately arranged with the transistor section in a predetermined first direction on the upper surface of the semiconductor substrate.

A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer with an outwardly exposed surface and an electrical insulating layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip, and a passive electrical component electrically connected to the upper electrically conductive layer of the lower carrier substrate.

A three-level I-type inverter includes first to fourth switching devices between first and second potentials, first to fourth diodes, and fifth and sixth diodes. The first to fourth diodes are respectively connected to the first to fourth switching devices in anti-parallel. Between a connection node of the first and second switching devices and a connection node of the third and fourth switching devices, the fifth and sixth diodes are connected in series and in anti-parallel with series connection of the second and third switching devices. A connection node of the fifth and sixth diodes is connected to an input node having intermediate potential. A connection node of the second and third switching devices is connected to an output node. The second switching device and diode are formed of a first reverse conducting IGBT. The third switching device and diode are formed of a second reverse conducting IGBT.

A semiconductor device includes a semiconductor substrate including a principal surface parallel to a plane defined by a first direction and a second direction substantially orthogonal to the first direction, and the principal surface having a first side parallel to the first direction; first unit transistors, each amplifying a first signal in a first frequency band to output a second signal; and second unit transistors, each amplifying the second signal to output a third signal and aligned in the second direction between the first side and a substrate center line in the first direction in plan view of the principal surface. A first center line in the first direction of a region in which the first unit transistors are aligned is farther from the first side than a second center line in the first direction of a region in which the second unit transistors are aligned.

A diode linearizer according to the present invention has parallelly mounting linearizer core units on a RF signal path via capacitors between the RF signal path and a ground, thus does not need a switch using an FET, for example, at a time of selectively operating a plurality of linearizer core units. Moreover, the diode linearizer does not need a capacitor in series for blocking a direct current between RF signal input and output terminals. Thus, a range of a gain which can be compensated by the diode linearizer can be increased. Furthermore, an insertion loss of the RF signal path in a state where the diode linearizer is off can be reduced, and a range of a gain expansion in operation can be increased. The switch is not used, or the number of elements of the capacitors which are needed is small, thus a circuit size is also small.