A thin-film integrated circuit comprising a first semiconductor device, a second semiconductor device, a first resistor, and a second resistor is provided. A semiconducting region of the first semiconductor device, a resistor body of the first resistor, a semiconducting region of the second semiconductor device, and a resistor body of the second resistor are formed from at least one of a first source material and a second source material, and a material of the resistor body of the first resistor and a material of the resistor body of the second resistor have different electrical properties.

A thin-film electronic component includes a first terminal, a second terminal, and a first current path between the first terminal and the second terminal, wherein the first current path is formed from a first segment of a first material and a first segment of a second material arranged in series between the first terminal and the second terminal.

Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.

The increasing power density and, therefore, current consumption of high performance integrated circuits (ICs) results in increased challenges in the design of a reliable and efficient on-chip power delivery network. In particular, meeting the stringent on-chip impedance of the IC requires circuit and system techniques to mitigate high frequency noise that results due to resonance between the package inductance and the onchip capacitance. In this paper, a novel circuit technique is proposed to suppress high frequency noise through the use of a hyperabrupt junction tuning varactor diode as a decoupling capacitor for noise critical functional blocks. With the proposed circuit technique, the voltage droops and overshoots on the onchip power distribution network are suppressed by up to 60% as compared to MIM or deep trench decoupling capacitors of the same capacitance. In addition, there is no added latency to react to power supply noise and there is no degradation to circuit performance as compared to existing techniques in commercial products and literature.

A protection device includes a first inductive element connecting first and second terminals and a second inductive element connecting third and fourth terminals. A first component includes a first avalanche diode connected in parallel with a first diode string, anodes of the first avalanche diode and a last diode in the string being connected to ground, cathodes of the first avalanche diode and a first diode in the string being connected, and a tap of the first diode string being connected to the first terminal. A second protection component includes a second avalanche diode connected in parallel with a second diode string, anodes of the second avalanche diode and a last diode in the string being connected to ground, cathodes of the second avalanche diode and a first diode in the string being connected, and a tap of the second diode string being connected to the third terminal.

A novel electric rectifier for use in a rectenna device is provided. The rectenna device can advantageously be used in a variety of applications. The electric rectifier comprises an integrated structure comprising: a diode structure comprising first and second electrodes located in first and second conductive layers respectively and an insulating layer between them, the diode structure being configured and operable for receiving an input signal and generating output signal indicative thereof, and a compensation structure electrically connected in parallel to said diode structure and being configured to compensate the parasitic capacitance of the diode structure when a frequency spectrum of the input signal is beyond the diode's cutoff frequency.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

A terahertz element of an aspect of the present disclosure includes a semiconductor substrate, first and second conductive layers, and an active element. The first and second conductive layers are on the substrate and mutually insulated. The active element is on the substrate and electrically connected to the first and second conductive layers. The first conductive layer includes a first antenna part extending along a first direction, a first capacitor part offset from the active element in a second direction as viewed in a thickness direction of the substrate, and a first conductive part connected to the first capacitor part. The second direction is perpendicular to the thickness direction and first direction. The second conductive layer includes a second capacitor part, stacked over and insulated from the first capacitor part. The substrate includes a part exposed from the first and second capacitor parts. The first conductive part has a portion spaced apart from the first antenna part in the second direction with the exposed part therebetween as viewed in the thickness direction.

A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

Voltage converter inlay modules are provided for embedding within a package substrate, and are configured to supply power to a processor, or similar digital circuit, which is mounted to the package substrate. The package substrate is typically mounted to a circuit board, or similar. The circuit board provides high-voltage, low-current power to the voltage converter module which, in turn, provides low-voltage high-current power to the processor. The voltage converter inlay provides largely vertical current conduction from the circuit board to the processor, thereby reducing conduction losses incurred by lateral current conduction. The location of the voltage converter inlay between the circuit board and the microprocessor minimizes radiation of electromagnetic interference. The number of terminals allocated for providing power to the package substrate may be minimized due to the voltage converter inlay inputting fairly low levels of current. The high-current power required by the processor is constrained within the package substrate.