Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.

A semiconductor device includes: a semiconductor substrate having a first conductivity-type drift region; a transistor portion; and a diode portion, wherein the transistor portion and the diode portion each have: a second conductivity-type base region; a plurality of trench portions penetrating the base region and having conductive portions provided therein; and a mesa portion sandwiched by trench portions, the transistor portion has one or more first conductivity-type accumulation regions that have doping concentrations higher than that of the drift region, the diode portion has one or more first conductivity-type high concentration regions that have doping concentrations higher than that of the drift region, and an integrated concentration of the doping concentrations of the accumulation regions is higher than an integrated concentration of the doping concentrations of the one or more high concentration regions of the mesa portion of the diode portion.

A method of forming an integrated circuit with a metal-insulator-poly (MIP) capacitor formed in a high-k metal gate (HKMG) process and the resulting device are provided. Embodiments include a device including a metal gate; a high-k dielectric layer formed around side walls of the metal gate, and a dummy polysilicon gate adjacent to at least one portion of the high-k dielectric layer. The device also includes a capacitor including the HK layer as an insulator, wherein the insulator is between a dummy as one electrode and the metal gate as another electrode.

According to an embodiment, a semiconductor device includes a first electrically conductive portion, a first semiconductor chip of a reverse-conducting insulated gate bipolar transistor, a second electrically conductive portion, a third electrically conductive portion, a second semiconductor chip of an insulated gate bipolar transistor, and a fourth electrically conductive portion. The first semiconductor chip includes a first electrode and a second electrode. The first electrode is electrically connected to the first electrically conductive portion. The second electrically conductive portion is electrically connected to the second electrode. The third electrically conductive portion is electrically connected to the first electrically conductive portion. The second semiconductor chip includes a third electrode and a fourth electrode. The third electrode is electrically connected to the third electrically conductive portion. The fourth electrically conductive portion is electrically connected to the fourth electrode and the second electrically conductive portion.

An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.

A method of forming an integrated circuit with a metal-insulator-poly (MIP) capacitor formed in a high-k metal gate (HKMG) process and the resulting device are provided. Embodiments include a device including a metal gate; a high-k dielectric layer formed around side walls of the metal gate, and a dummy polysilicon gate adjacent to at least one portion of the high-k dielectric layer. The device also includes a capacitor including the HK layer as an insulator, wherein the insulator is between a dummy as one electrode and the metal gate as another electrode.

An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.

A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.

A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.