An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

A method for coating a multi-layered polymer film is disclosed including coating a first layer of polyimide onto a carrier, curing the first layer of polyimide by subjecting the first layer of polyimide to an elevated temperature, depositing a first layer of metal onto the cured first layer of polyimide, coating a second layer of polyimide onto the first layer of metal, and curing the second layer of polyimide by subjecting the second layer of polyimide to an elevated temperature. A flexible electronic device is also disclosed, including multiple interposed layers of polyimide and layers of metal, a dielectric barrier layer disposed on the top layer of polyimide, and a thin film transistor-based device disposed on the dielectric barrier layer. The flexible electronic device has little to no curl.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

Provided are a micro light source array for a display device, a display device including the micro light source array, and a method of manufacturing the display device. The micro light source array includes: a plurality of silicon sub-mounts provided on a substrate, each silicon sub-mount from among the plurality of silicon sub-mounts corresponding to a respective sub-pixel from among a plurality of sub-pixels of a display device, the plurality of silicon sub-mounts being separated from each other by a plurality of trenches; a plurality of light emitting device chips coupled to the plurality of silicon sub-mounts; and a plurality of driving circuits provided at the plurality of silicon sub-mounts.

A flexible display motherboard and a manufacturing method thereof are provided. The flexible display motherboard includes a carrier substrate and a flexible display panel unit formed thereon. The flexible display panel unit includes a flexible base formed on the carrier substrate, and a display region and a periphery region which are positioned on the flexible base. A display device is formed in the display region, and the periphery region surrounds the display region. The flexible display panel unit further includes a dissolvable layer positioned between the carrier substrate and the flexible base. The dissolvable layer is formed at least in an area corresponding to the display region. The dissolvable layer is dissolvable in a solvent.

A method of producing a CF board and an array board includes: a separation film forming process for forming resin substrates on the separation films; a thin film component forming process for forming TFTs and color filters that axe thin film components on the resin removals of fee resin substrates; a determining process for determining whether levels of adhesion between the separation films and the resin substrates are high or low based on image data obtained through capturing of images of the separation films, and a removing process for removing the resin substrates from the supporting substrates if the levels of adhesion are determined low in the determining process.

There is set forth herein an optoelectrical device, comprising: a substrate; an interposer dielectric stack formed on the substrate, the interposer dielectric stack including a base interposer dielectric stack, a photonics device dielectric stack, and a bond layer that integrally bonds the photonics device dielectric stack to the base interposer dielectric stack. There is set forth herein a method comprising building an interposer base structure on a first wafer having a first substrate, including fabricating a plurality of through vias in the first substrate and fabricating within an interposer base dielectric stack formed on the first substrate one or more metallization layers; and building a photonics structure on a second wafer having a second substrate, including fabricating one or more photonics devices within a photonics device dielectric stack formed on the second substrate.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing a second lithography step on the third level; perform processing steps to form first memory cells within the second level and second memory cells within the third level, where first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and deposit a gate electrode for the second and the third transistors simultaneously.