A reinforced thin-film device (100, 200, 500) including a substrate (101) having a top surface for supporting an epilayer; a mask layer (103) patterned with a plurality of nanosize cavities (102, 102′) disposed on said substrate (101) to form a needle pad; a thin-film (105) of lattice-mismatched semiconductor disposed on said mask layer (103), wherein said thin-film (105) comprises a plurality of in parallel spaced semiconductor needles (104, 204) of said lattice-mismatched semiconductor embedded in said thin-film (105), wherein said plurality of semiconductor needles (104, 204) are substantially vertically disposed in the axial direction toward said substrate (101) in said plurality of nanosize cavities (102, 102′) of said mask layer (103), and where a lattice-mismatched semiconductor epilayer (106) is provided on said thin-film supported thereby.

An InN nanorod epitaxial wafer grown on an aluminum foil substrate (1) sequentially comprises the aluminum foil substrate (1), an amorphous aluminum oxide layer (2), an AlN layer (3) and an InN nanorod layer, (4) from bottom to top. The wafer can be prepared by pretreating the aluminum foil substrate with an oxidized surface and carrying out an in-situ annealing treatment; then, in a molecular beam epitaxial growth process, forming AlN nucleation sites on the annealed aluminum foil substrate, nucleating on the AlN and growing InN nanorods on the AlN, where the substrate temperature is 400-700° C., the pressure of a reaction chamber is 4.0-10.0×10.sup.−5 Torr and the beam ratio of V/III is 20-40.

The semiconductor device includes a first source/drain layer, a dielectric layer, a channel, a gate electrode, a first gate dielectric layer, a seed layer, a conductive layer, and a second source/drain layer. The dielectric layer is disposed on the first source/drain layer, in which the dielectric layer has a hole penetrating the dielectric layer. The channel is disposed in the hole and extends substantially perpendicular to an upper surface of the first source/drain layer. The gate electrode surrounds the channel. The first gate dielectric layer is disposed between the gate electrode and the channel. The seed layer is disposed between the gate electrode and the dielectric layer and on an upper surface of the dielectric layer, in which the seed layer covers a portion of a sidewall of the hole.

A semiconductor structure includes a nanofog oxide adhered to an inert 2D or 3D surface or a weakly reactive metal surface, the nanofog oxide consisting essentially of 0.5-2 nm Al.sub.2O.sub.3 nanoparticles. The nanofog can also consists of sub 1 nm particles. Oxide layers can be formed on the nanofog, for example a bilayer stack of Al.sub.2O.sub.3—HfO.sub.2. Additional examples are from the group consisting of ZrO.sub.2, HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2, ZrTiO.sub.2, HfTiO.sub.2, La.sub.2O.sub.3, Y.sub.2O.sub.3, Ga.sub.2O.sub.3, GdGaOx, and alloys thereof, including the ferroelectric phases of HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2. The structure provides the basis for various devices, including MIM capacitors, FET transistors and MOSCAP capacitors.

A method for manufacturing a quantum electronic circuit includes etching a semiconducting layer so as to obtain: a plurality of pillars; and a qubit layer; oxidising the flank of each pillar; forming coupling rows and coupling columns; and depositing separation layers leaving a contact surface protrude from each pillar.

Disclosed are novel structures and methods for 3D CMOS integrated circuits built with vertical transistors. A gate extension is selectively patterned by first patterning a sacrificial dielectric disposed on a gate material. A 3D CMOS IC comprises vertical transistors of one type constructed in one level and those of an opposite type in another level. The gate of lower-level vertical transistors may be coupled to a top interconnect directly through a 3D gate contact or indirectly through an upper-level via and a lower-level contact. A common-gate coupling may be formed between vertical transistors in different levels through a strapping contact or a gate via. A common-drain coupling may be formed between vertical transistors in different levels by forming upper-level vertical transistor on a piece of conductive film disposed over lower-level vertical transistor with or without an intervening top contact for lower-level vertical transistor.

A vertical metal oxide semiconductor field effect transistor (MOSFET) and a method for forming a vertical MOSFET is presented. The MOSFET comprises: a top contact; a bottom contact; a nanowire (602) forming a charge transport channel between the top contact and the bottom contact; and a wrap-around gate (650) enclosing the nanowire (602) circumference, the wrap-around gate (650) having an extension spanning over a portion of the nanowire (602) in a longitudinal direction of the nanowire (602), wherein the wrap-around gate (650) comprises a gate portion (614) and a field plate portion (616) for controlling a charge transport in the charge transport channel, and wherein the field plate portion (616) is arranged at a first radial distance (636) from the center of the nanowire (602) and the gate portion (614) is arranged at a second radial distance (634) from the center of the nanowire (602); characterized in that the first radial distance (636) is larger than the second radial distance (634).

A MIM energy storage device comprising a bottom electrode; a plurality of electrically conductive vertical nanostructures; a bottom conduction-controlling layer conformally coating each nanostructure in the plurality of electrically conductive vertical nanostructures; and a layered stack of alternating conduction-controlling layers and electrode layers conformally coating the bottom conduction-controlling layer, the layered stack including at least a first odd-numbered electrode layer at a bottom of the layered stack, a first odd-numbered conduction-controlling layer directly on the first odd-numbered electrode layer, and a first even-numbered electrode layer directly on the first odd-numbered conduction-controlling layer. Each even-numbered electrode layer in the layered stack is electrically conductively connected to the bottom electrode; and each odd-numbered electrode layer in the layered stack is electrically conductively connected to any other odd-numbered electrode layer in the layered stack.

A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate. The plurality of fins each include a first portion having a first width, and a second portion having a second width greater than the first width. The method also includes forming a sacrificial layer on the substrate in a space between a first fin and a second fin of the plurality of fins, wherein the first fin and the second fin correspond to a vertical transistor. In the method, lower portions of the first and second fins are removed, and an epitaxial region is formed under remaining portions of the first and second fins. The sacrificial layer is removed from the space between the first fin and the second fin after forming the epitaxial region.

A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.