The present disclosure provides a transistor device and a semiconductor layout structure. The transistor device includes an active region disposed in a substrate, a gate structure disposed over the active region, and a source/drain region disposed at two opposite sides of the gate structure. The active region includes a first region including a first length, a second region including a second length less than the first length, and a third region between the first region and the second region. The gate structure includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction. The first portion is disposed over at least the third region of the active region, and the second portion is disposed over at least a portion of the third region and a portion of the second region.

The field effect transistor device comprises a substrate (1) of semiconductor material, a body well of a first type of electric conductivity in the substrate, a source region in the body well, the source region having an opposite second type of electric conductivity, a source contact (3) on the source region, a body contact region of the first type of electric conductivity in the body well, a body contact (5) on the body contact region, and a gate electrode layer (2) partially overlapping the body well. A portion (2*) of the gate electrode layer (2) is present between the source contact (3) and the body contact (5).

A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer;

patterning the first dielectric layer into a first sublayer of a gate dielectric layer;

converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is lower than a top surface of the substrate, depositing a gate electrode layer over the substrate and patterning the gate electrode layer to form a first gate electrode region and a second gate electrode region, wherein the second gate electrode region is vertically aligned with the first isolation region and the first gate electrode region is immediately adjacent to the second gate electrode region.

A semiconductor device, includes a first conductive type first doping area, a second conductive type second doping area, a source region, a drain region, a gate insulating film, and a gate electrode. The first conductive type first doping area is formed in a substrate region. The second conductive type second doping area is formed in the substrate to be spaced apart from the first conductive type first doping area. The source region is formed in the first conductive type first doping area. The drain region is formed in the second conductive type second doping area. The gate insulating film is formed between the source region and the drain region. A thickness of a first end of the gate insulating film is different than a thickness of a second end of the gate insulating film. The gate electrode formed on the gate insulating film.

A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is level with a top surface of the substrate, removing an upper portion of the first isolation region to form a recess, depositing a gate dielectric layer over the first isolation region, forming a gate electrode layer over the gate dielectric layer and patterning the gate electrode layer to form a gate electrode region, wherein a first portion of the gate electrode region is vertically aligned with the first isolation region and a second portion of the gate electrode region is formed over the substrate, and where a top surface of the first portion is lower than a top surface of the second portion.

Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed on a substrate. A first well of a first conductivity type is arranged partially in the substrate and partially in the first fin. A second well of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. First and second source/drain regions of the second conductivity type are respectively formed within the first well in the first fin and within the second well in the second fin. Spaced-apart gate structures are formed that overlap with respective portions of the first fin. A doped region of the first conductivity type is arranged within the second well in the first fin between the first and second gate structures.

A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.