A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.

Provided is a semiconductor device whose performance is improved. A p type body region is formed in an n type semiconductor layer containing silicon carbide, and a gate electrode is formed on the body region with a gate insulating film interposed therebetween. An n type source region is formed in the body region on a side surface side of the gate electrode, and the body region and a source region are electrically connected to a source electrode. A p type field relaxation layer FRL is formed in the semiconductor layer on the side surface side of the gate electrode, and the source electrode is electrically connected to the field relaxation layer FRL. The field relaxation layer FRL constitutes a part of the JFET 2Q which is a rectifying element, and a depth of the field relaxation layer FRL is shallower than a depth of the body region.

Example embodiments relate to a field-effect transistors having improved layouts. One example field-effect transistor includes a semiconductor substrate on which at least one transistor cell array is arranged. Each transistor cell includes a first transistor cell unit. Each first transistor cell unit includes a plurality of gate fingers, a main gate finger segment, a plurality of drain fingers, and a main drain finger segment. Each first transistor cell unit also includes a main gate finger base connected to the main gate finger segment of the first transistor cell unit and extending from that main gate finger segment towards the main drain finger segment of that first transistor cell unit. Further, each first transistor cell unit includes a main drain finger base connected to the main drain finger segment of that first transistor cell and extending from that main drain finger segment towards that main gate finger segment.

A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

A method of manufacturing an insulated gate semiconductor device includes simultaneously forming a gate trench and a contact trench that respectively penetrate form a top of the electrode contact region through a main electrode contact region and a injection control region in a depth direction and respectively reach a charge transport region, the contact trench being disposed at a position laterally separated from the gate trench in a plan view; and embedding a gate electrode inside the gate trench with a gate insulating film interposed therebetween, thereby forming an insulated gate structure, and simultaneously embedding an injection suppression region inside the contact trench, the gate electrode and the injection suppression region being both made of a second semiconductor material having a narrower bandgap than a bandgap of the first semiconductor material of the charge transport region.

A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.

In one aspect, a double-diffused metal oxide semiconductor (DMOS) includes a region of a semiconductor having a first region of a semiconductor having a first-type dopant, a first well having a second-type dopant, a dielectric within the first well, the dielectric having a bottom surface and a top surface opposite the bottom surface, a gate disposed on the top surface of the dielectric. The gate, the dielectric and the first well are configured to form a first reduced surface field (RESURF). The bottom surface of the dielectric has a first portion and a second portion, and the first portion of the bottom surface of the dielectric is closer to the top surface of the dielectric than the second portion of the bottom surface of the dielectric.

A power semiconductor including a gate, a source, a plurality of first long-strip source metal layer, a drain and a plurality of second long-strip drain metal layer is provided. The source includes a first copper particle layer and a first metal layer that covers the bottom surface of the first copper particle layer. The source is bonded to the first long-strip source metal layer via a first metal pillar. The drain includes a second copper particle layer and a second metal layer that covers the bottom surface of the second copper particle layer. The drain is bonded to the second long-strip drain metal layer via a second metal pillar. The thickness of the first copper particle layer and the second copper particle layer are 5 μm˜100 μm. The first copper particle layer and the second copper particle layer are formed by plating and stacking a plurality of large-grain copper.

A power semiconductor including a gate, a source, a plurality of first long-strip source metal layer, a drain and a plurality of second long-strip drain metal layer is provided. The source includes a first copper particle layer and a first metal layer that covers the bottom surface of the first copper particle layer. The source is bonded to the first long-strip source metal layer via a first metal pillar. The drain includes a second copper particle layer and a second metal layer that covers the bottom surface of the second copper particle layer. The drain is bonded to the second long-strip drain metal layer via a second metal pillar. The thickness of the first copper particle layer and the second copper particle layer are 5 μm˜100 μm. The first copper particle layer and the second copper particle layer are formed by plating and stacking a plurality of large-grain copper.

A power semiconductor is provided. The power semiconductor includes a gate, a source, a silicon chip and a drain. The source includes a first copper particle layer and a first metal layer. The first copper particle layer covers the upper surface of the first metal layer. The silicon chip is bonded to the lower surface of the first metal layer. The drain is bonded to the lower surface of the silicon chip. The thickness of the first copper particle layer is greater than the thickness of the first metal layer. All copper mentioned are of large grain copper with size greater than 0.25 um.