A compound semiconductor layer in a semiconductor device includes a drift region of a first conductivity type, a JFET region of the first conductivity type disposed above the drift region, a body region of a second conductivity type disposed above the drift region and adjacent to the JFET region, and a JFET embedded region of the second conductivity type or i-type disposed in the JFET region. The JFET region has a bottom surface portion adjacent to the drift region, a side surface portion adjacent to the body region, and an inside portion adjacent to the JFET embedded region, and further has a high concentration portion at the bottom surface portion and the side surface portion. The high concentration portion has an impurity concentration higher than an impurity concentration of the inside portion.

A semiconductor device with a junction type FET includes: a drift layer; a channel layer on the drift layer; a source layer in a surface portion of the channel layer; a gate layer in the channel layer; a body layer in the channel layer; a drain layer disposed on an opposite side of the source layer with respect to the drift layer; a gate wiring electrically connected to the gate layer; a first electrode electrically connected to the source layer and the body layer; and a second electrode electrically connected to the drain layer.

A trench junction field effect transistor (trench JFET) includes a mesa region confined by first and second trenches along a first lateral direction. The first and second trenches extend into a semiconductor body from a first surface of the semiconductor body. A mesa channel region of a first conductivity type is confined, along the first lateral direction, by first and second gate regions of a second conductivity type. A first pn junction is defined by the mesa channel region and the first gate region. A second pn junction is defined by the mesa channel region and the second gate region. The mesa channel region includes, along the first lateral direction, first, second and third mesa channel sub-regions having a same extent along the first lateral direction.

A fabrication method of forming a silicon carbide MOSFET is provided. The fabrication method includes the step of providing a semiconductor substrate. A P-well region is formed by implanting the semiconductor substrate through the P-well mask. A spacer is disposed on sidewall of the P-well mask and the P-well region is implanted to form a P-plus layer and an N-plus layer. A gate oxide layer, a poly gate and a first interlayer dielectric layer are formed on the semiconductor substrate. The first interlayer dielectric layer is etched to form an opening and the opening exposes the P-plus layer. A metal layer is disposed to cover the opening and the first interlayer dielectric layer.

A method of forming an alignment contact includes: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.

A semiconductor device includes a junction field effect transistor (JFET) on a silicon-on-insulator (SOI) substrate. The JFET includes a gate with a first gate segment contacting the channel on a first lateral side of the channel, and a second gate segment contacting the channel on a second, opposite, lateral side of the channel. The first gate segment and the second gate segment extend deeper in the semiconductor layer than the channel. The JFET further includes a drift region contacting the channel, and may include a buried layer having the same conductivity type as the channel, extending at least partway under the drift region.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An amplifier is provided. The amplifier includes a first resistor electrically connected to the input terminal, a second resistor electrically connected to the output terminal, a switch including a metal-oxide-semiconductor field-effect transistor (MOSFET) and electrically connected to one end of the second resistor, and a switch control processor configured to electrically connect the gate terminal of the MOSFET constituting the switch and the bulk terminal of the MOSFET constituting the switch to an impedance having an impedance value higher than a preset first threshold.

Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO.sub.2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO.sub.2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

A compound semiconductor layer in a semiconductor device includes a drift region of a first conductivity type, a JFET region of the first conductivity type disposed above the drift region, a body region of a second conductivity type disposed above the drift region and adjacent to the JFET region, and a JFET embedded region of the second conductivity type or i-type disposed in the JFET region. The JFET region has a bottom surface portion adjacent to the drift region, a side surface portion adjacent to the body region, and an inside portion adjacent to the JFET embedded region, and further has a high concentration portion at the bottom surface portion and the side surface portion. The high concentration portion has an impurity concentration higher than an impurity concentration of the inside portion.