Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.

An electronic device can include a JFET that can include a drain contact region, a channel region spaced apart from the drain contact region, and a gate region adjacent the channel region. In an embodiment, the gate region includes a relatively heavier doped portion and a relatively lighter portion closer to the drain contact region. In another embodiment, a gate field electrode can be extended beyond a field isolation structure and overlie a channel of the JFET. In a further embodiment, a region having relatively low dopant concentration can be along the drain side of the conduction path, where the region is between two other more heavily doped regions. In another embodiment, alternating conducting channel and gate regions can be used to allow lateral and vertical pinching off of the conducting channel regions.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

A method of forming a buried implanted region in a silicon carbide semiconductor layer includes implanting first dopant ions into the silicon carbide semiconductor layer at a first dose and first implant energy to form a first channelized doping profile having a first de-channeled peak at a first depth in the silicon carbide semiconductor layer and a first channeled peak at a second depth that is greater than the first depth. Second dopant ions are implanted into the silicon carbide semiconductor layer at a second dose and second implant energy to form a second channelized doping profile. The second channelized doping profile has a second channeled peak at a third depth in the silicon carbide semiconductor layer that is between the first depth and the second depth. The first channelized doping profile and the second channelized doping profile form a combined doping profile that defines the buried implanted region.

Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal.

Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

A semiconductor device includes: a semiconductor body with an edge region arranged between an inner region and an edge surface; a first semiconductor region of a first doping type in the inner region; and a second semiconductor region of a second doping type in the inner and edge regions. An edge termination structure includes: a third semiconductor region in the edge region adjoining the first semiconductor region; a surface section of the second semiconductor region adjoining a first main surface of the semiconductor body; and an amorphous passivation layer having a specific resistance higher than 10.sup.9 cm adjoining the third semiconductor region and the surface section. An electrically active doping dose of the third region at a lateral position spaced apart from the first region by 50% of a width of the edge termination structure is at least Q.sub.BR/q, wherein Q.sub.BR is breakdown charge and q is elementary charge.

Described is a semiconductor device including a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region, a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region, and a first gate electrode and a second gate electrode disposed spaced apart from the drain region. A maximum vertical length of the source region in a direction vertical to the first or second gate electrode is greater than a maximum vertical length of the drain region in the direction in a plan view.

A junction field effect transistor includes a first semiconductor layer of first conductivity type, an element isolation insulator disposed on the first semiconductor layer to partition an active area, a second semiconductor layer of second conductivity type, on the first semiconductor layer in the active area, and having an end in a first direction separated from the element isolation insulator, a source layer of second conductivity type, on the second semiconductor layer, the source layer having an impurity concentration higher than that of the second semiconductor layer, a drain layer of second conductivity type, on the second semiconductor layer, and separated from the source layer in a second direction, the drain layer having an impurity concentration higher than that of the second semiconductor layer, and a gate layer of first conductivity type, on the second semiconductor layer, and between and separated from the source and drain layers.

The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE).

An amplifier is provided. The amplifier includes a first resistor electrically connected to the input terminal, a second resistor electrically connected to the output terminal, a switch including a metal-oxide-semiconductor field-effect transistor (MOSFET) and electrically connected to one end of the second resistor, and a switch control processor configured to electrically connect the gate terminal of the MOSFET constituting the switch and the bulk terminal of the MOSFET constituting the switch to an impedance having an impedance value higher than a preset first threshold.