A semiconductor device according to the present invention includes a substrate having a cell portion and a terminal portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface electrode provided on the back surface of the substrate, the surface structure includes a convex portion protruding upward above the cell portion, and at least a part of the cell portion is thinner than the terminal portion.

In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 510.sup.15 cm.sup.3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.510.sup.15 cm.sup.3, thickness: about 100 nm, sheet concentration: 4.510.sup.10 cm.sup.2), and an n-type GaAs layer Si concentration: about 510.sup.15 cm.sup.3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 110.sup.11 cm.sup.2.

Disclosed are a GaN power device and a manufacturing method thereof. The GaN power device includes a substrate, and a buffer layer, a GaN channel layer and a barrier layer sequentially stacked on the substrate from bottom to top. The barrier layer is provided with a p-GaN cap layer and a p-GaN thin layer, and the p-GaN thin layer is configured to cover the surface of the barrier layer and is connected to the p-GaN cap layer; the upper surface of the barrier layer is also provided with an input electrode and an output electrode, and a control electrode is provided on the upper surface of the p-GaN cap layer. The control electrode and the p-GaN thin layer are located between the input electrode and the output electrode.

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

A switch LNA module including a silicon on insulator, SOI, wafer having a silicon substrate and an active layer separated by a buried oxide, BOX, layer, wherein the SOI substrate is a high resistance, HR, SOI substrate having a silicon handle wafer with a resistivity greater than 1 k?-cm. The switch LNA module further includes a switch having a plurality of SOI transistors, a low noise amplifier, LNA, located in the SOI wafer and connected to an output of the switch. The LNA includes a bipolar transistor formed in a bulk region of the SOI wafer where the BOX layer is removed. The switch LNA module further includes a thick metal layer for connecting to the switch and to the LNA.

An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a semiconductor layer, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.

An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a semiconductor layer, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.

A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.