A semiconductor device according to the present invention includes a substrate having a cell portion and a terminal portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface electrode provided on the back surface of the substrate, the surface structure includes a convex portion protruding upward above the cell portion, and at least a part of the cell portion is thinner than the terminal portion.

A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.

A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.

In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 510.sup.15 cm.sup.3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.510.sup.15 cm.sup.3, thickness: about 100 nm, sheet concentration: 4.510.sup.10 cm.sup.2), and an n-type GaAs layer Si concentration: about 510.sup.15 cm.sup.3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 110.sup.11 cm.sup.2.

A logic gate cell structure is disclosed. The logic gate cell structure includes a substrate, a channel layer disposed over the substrate, and a field-effect transistor (FET) contact layer disposed over the channel layer. The FET contact layer is divided by an isolation region into a single contact region and a combined contact region. The channel layer and the FET contact layer form part of a FET device. A collector layer is disposed within the combined contact region over the FET contact layer to provide a current path between the channel layer and the collector layer though the FET contact layer. The collector layer, a base layer, and an emitter layer form part of a bipolar junction transistor.

In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 510.sup.15 cm.sup.3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.510.sup.15 cm.sup.3, thickness: about 100 nm, sheet concentration: 4.510.sup.10 cm.sup.2), and an n-type GaAs layer Si concentration: about 510.sup.15 cm.sup.3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 110.sup.11 cm.sup.2.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a first P-type semiconductor layer is provided, and an N-type semiconductor layer and a second P-type semiconductor layer are formed in sequence on the first P-type semiconductor layer. The first P-type semiconductor layer, the N-type semiconductor layer and the second P-type semiconductor layer all include a GaN-based material. When the first P-type semiconductor layer is provided, its upper surface is controlled to be a Ga surface; when the N-type semiconductor layer is formed, its upper surface is controlled to be an N surface; when the second P-type semiconductor layer is formed, its upper surface is controlled to be an N surface.

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.