A power control switch assembly. The assembly may include a thyristor device, where the thyristor device includes a first device terminal, a second device terminal, and a gate terminal> The assembly may include a negative temperature coefficient (NTC) device, electrically coupled to the gate terminal of the thyristor device on a first end, and electrically coupled to the first device terminal of the thyristor device on a second end, wherein the NTC device is thermally coupled to the thyristor device.

The present disclosure relates to semiconductor structures and, more particularly, to bi-directional silicon controlled rectifiers (SCRs) and methods of manufacture. The structure includes: a plurality of diffusion regions; a plurality of p-type (P+) wells adjacent to the diffusion regions, wherein the P+ wells are directly connected; and a plurality of n-type (N+) wells adjacent to the P+ wells.

A silicon-controlled-rectifier electrostatic protection structure and a fabrication method are provided. The structure includes: a substrate of P-type; a first N-type well; a second N-type well; a third N-type well; an anode P-type doped region in the first N-type well; second N-type doped regions at sides of the first N-type well; first P-type doped regions at sides of the first N-type well; third N-type doped regions at sides of the first N-type well; gate structures and fourth N-type doped regions at the sides of the first N-type well; and fifth N-type doped regions at the sides of the first N-type well. The fourth N-type doped regions and the third N-type doped regions are disposed at sides of each of the gate structures along a first direction respectively.

A one-way switch has a gate referenced to a main back side electrode. An N-type substrate includes a P-type anode layer covering a back side and a surrounding P-type wall. First and second P-type wells are formed on the front side of the N-type substrate. An N-type cathode region is located in the first P-type well. An N-type gate region is located in the second P-type well. A gate metallization covers both the N-type gate region and a portion of the second P-type well. The second P-type well is separated from the P-type wall by the N-type substrate except at a location of a P-type strip that is formed in the N-type substrate and connects a portion on one side of the second P-type well to an upper portion of said P-type wall.

A power switching device may include a semiconductor substrate and a body region comprising an n-type dopant, the body region disposed in an inner portion of the semiconductor substrate; a first base layer disposed adjacent a first surface of the semiconductor substrate, the first p-base layer comprising a p-type dopant; a second base layer disposed adjacent a second surface of the semiconductor substrate, the second base layer comprising a p-type dopant; a first emitter region, disposed adjacent the first surface of the semiconductor substrate, the first emitter region comprising a n-type dopant; a second emitter-region, disposed adjacent the second surface of the semiconductor substrate, the second emitter-region comprising a n-type dopant; a first field stop layer arranged between the first base layer and the body region, the first field stop layer comprising a n-type dopant; and a second field stop layer arranged between the second base layer and the body region, the second field stop layer comprising a n-type dopant.

Bi-directional trench power switches. At least one example is a semiconductor device comprising: an upper base region associated with a first side of a substrate of semiconductor material; an upper-CE trench defined on the first side, the upper-CE trench defines a proximal opening at the first side and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper-CE trench; a lower base region associated with a second side of substrate; and a lower collector-emitter region associated with the second side.

Bi-directional trench power switches. At least one example is a semiconductor device comprising: an upper base region associated with a first side of a substrate of semiconductor material; an upper-CE trench defined on the first side, the upper-CE trench defines a proximal opening at the first side and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper-CE trench; a lower base region associated with a second side of substrate; and a lower collector-emitter region associated with the second side.

The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the B-TRAN type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

A semiconductor device includes a semiconductor substrate having a first surface and a second surface, first to eighth regions, a first thyristor, and a second thyristor. The seventh region with the impurity concentration higher than that of the first region is formed in the first region while being apart from the sixth region electrically connected to the gate electrode, and being electrically connected to the first electrode. The eighth region with the impurity concentration higher than that of the third region is formed in contact with the second surface side of the third region and the fourth region, and with the second surface, while being electrically connected to the fourth region by the second electrode. The seventh region has the impurity concentration higher than that of the first region. The eighth region has the impurity concentration higher than that of the third region.

A power control switch assembly. The assembly may include a thyristor device, where the thyristor device includes a first device terminal, a second device terminal, and a gate terminal> The assembly may include a negative temperature coefficient (NTC) device, electrically coupled to the gate terminal of the thyristor device on a first end, and electrically coupled to the first device terminal of the thyristor device on a second end, wherein the NTC device is thermally coupled to the thyristor device.