An electronic device includes an ESD protection device with implanted regions that extend around a finger shape with a straight portion and elongated turn portions, and contacts that extend only in the straight portion, where the turn portions include elongated lightly doped implanted regions to mitigate turn on of a curvature PNP transistor for uniform device breakdown performance. Adjacent finger structures are spaced apart from one another to mitigate thermal transfer between device fingers.

An electronic device includes a silicon-on-insulator (SOI) structure, and an electrostatic discharge (ESD) protection device, with an isolation layer having a thickness and extending in a trench from a first implanted region. The ESD protection device includes a conductive field plate that extends over a portion of the first implanted region and past the first implanted region and over a portion of the isolation layer by an overlap distance that is 3.5 to 5.0 times the thickness of the isolation layer. In one example, the ESD protection device has a finger or racetrack shape, and the first implanted region and a second implanted region extend around first and second turn portions of the finger shape.

An electronic device includes an ESD protection device with implanted regions that extend around a finger shape with a straight portion and elongated turn portions, and contacts that extend only in the straight portion, where the turn portions include elongated lightly doped implanted regions to mitigate turn on of a curvature PNP transistor for uniform device breakdown performance. Adjacent finger structures are spaced apart from one another to mitigate thermal transfer between device fingers.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.