A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.

Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

The present disclosure provides a silicon-controlled rectifier structure and a manufacturing method therefor. The silicon-controlled rectifier structure comprises a substrate; and an N-Well and a P-Well in the substrate, and an N-type heavily-doped region and a P-type heavily-doped region which are connected to an anode are provided in the N-Well, and a guard ring connected to the anode is further provided in the N-Well between the N-type heavily-doped region and the P-type heavily-doped region, the guard ring being spaced from the N-type heavily-doped region by a shallow trench isolation, and an active area having a predetermined width exists between the guard ring and the P-type heavily-doped region; and an N-type heavily-doped region and a P-type heavily-doped region which are connected to a cathode are provided in the P-Well.

SCRs are a must for ESD protection in low voltagehigh speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

An electrostatic discharge protection device includes: a substrate of a second conductivity type, the substrate including a well of a first conductivity type; a cathode electrode connected to the substrate; a first diffusion region of the second conductivity type and a second diffusion region of the first conductivity type, formed in the substrate and connected to the cathode electrode; an anode electrode connected to the substrate; a third diffusion region of the second conductivity type and a fourth diffusion region of the first conductivity type, formed in the well and connected to the anode electrode; a fifth diffusion region of the first conductivity type, formed on a border of the substrate and the well; and a sixth diffusion region of the first conductivity type, formed in the substrate between the first and second diffusion regions and the fifth diffusion region and configured to receive a bias voltage from outside.

The invention relates to a turn-off power semiconductor device comprising a plurality of thyristor cells, each thyristor cell comprising a cathode region; a base layer; a drift layer; an anode layer; a gate electrode which is arranged lateral to the cathode region in contact with the base layer; a cathode electrode; and an anode electrode. Interfaces between the cathode regions and the cathode electrodes as well as interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar. In addition, the base layer includes a gate well region extending from its contact with the gate electrode to a depth, which is at least half of the depth of the cathode region, wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 m from the cathode region. The base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4.

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.