Provided is a semiconductor device includes a first semiconductor layer provided on a first main surface of the semiconductor substrate, a plurality of first semiconductor regions selectively provided at upper layer parts of the semiconductor layer, a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region, a gate insulating film covering the first semiconductor regions and the second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film, a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region being exposed to a bottom part thereof, a first main electrode provided on the interlayer insulating film, and configured to electrically connect to the second semiconductor region via the contact hole, and a second main electrode provided on a second main surface of the semiconductor substrate.

A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use high voltage transistors within a SiC layer that are coupled with one or more transistors in one or more other layers in a cascode format in order to switch the high voltage transistors in the SiC layer using low voltages. Other embodiments may be described and/or claimed.

Vertical junction field-effect transistors (VJFETs) with integrated source-drain anti-parallel diodes are described. In an embodiment, a trench VJFET with integrated source-drain anti-parallel diodes structure is coupled with a low-voltage metal oxide semiconductor field-effect transistor (MOSFET) in a dual gate cascode configuration.

This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a Gap Filler layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The Gap Filler layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

Hot metal dissolution of carbon atoms is used to structure a diamond substrate. A layer of catalytic material is deposited on at least a portion of a surface of the diamond substrate. The layer of catalytic material may be structured using photolithography to define a gap exposing the surface of the diamond substrate, where the gap has a (110) orientation relative to the crystal structure of the diamond substrate. The exposed surface of the diamond substrate is etched to form at least one recess having at least one (111) oriented diamond surface (facet). The catalytic material is removed by a suitable cleaning process. The (111) oriented surface is then overgrown with diamond comprising a dopant resulting in a conductivity of the overgrown diamond that is different from the conductivity of the doped substrate. The doping concentration of the overgrown diamond is greater than 10.sup.19 cm.sup.3.

Manufacturing methods of JFET-type compact three-dimensional memory (3D-M.sub.C) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.

A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.

A power semiconductor device including a semiconductor layer having a first conductivity type and configured to include a protrusion formed from an upper region of the semiconductor layer to partially protrude upward, a shielding region having a second conductivity type opposite to the first conductivity type and disposed within the protrusion and configured to contact a top surface of the protrusion, a gate insulation layer disposed on the semiconductor layer and configured to cover the protrusion and to come into contact with the shielding region, and a gate electrode layer disposed on the gate insulation layer.

A semiconductor device is provided with: a source wiring electrically coupled to the source electrode of a transistor; a drain wiring electrically coupled to the drain electrode of the transistor; a source pad electrically coupled to the source wiring; and, a drain pad electrically coupled to the drain wiring. The source wiring includes a first source wiring section and a second source wiring section having a width greater than that of the first source wiring section. The drain wiring includes a first drain wiring section and a second drain wiring section having a width greater than that of the first drain wiring section. The source pad at least partially overlaps the second drain wiring section in plan view. The drain pad at least partially overlaps the second source wiring section in plan view.