A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer is described. The SOI wafer includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer. The method includes: forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions. Various devices produced according to the method are also described.

A semiconductor device is disclosed herein. The semiconductor device includes a silicon carbide substrate, trench structures, mesa structures, a first oxide layer, a conductive layer, a second oxide layer, a dielectric layer, and an insulation layer. The trench structures are formed on a surface of the silicon carbide substrate. Each trench structure has sidewalls and a bottom, and each respective mesa structure is formed between the respective adjacent trench structures. The first oxide layer is formed on the sidewalls of the trench structures. The conductive layer is formed on the bottom of the trench structures and on a top surface of each mesa structure. The second oxide layer is formed on the first oxide layer and the conductive layer. The dielectric layer is formed on the second oxide layer. The insulation layer is formed on the dielectric layer.

Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a source doped region, a drain doped region, and a lightly doped region and an intrinsic region that are arranged adjacent to each other and located between the source doped region and the drain doped region. The lightly doped region is adjacent to the source doped region, and the intrinsic region is adjacent to the drain doped region. A doping concentration of the source doped region and the drain doped region is greater than a doping concentration of the lightly doped region.

A semiconductor device includes a semiconductor element. The semiconductor element has a semiconductor layer, a first-conductivity-type layer, a saturation current suppression layer, a current dispersion layer, a base region, a source region, trench gate structures, an interlayer insulation film, a source electrode, a drain electrode, and a second deep layer. The first-conductivity-type layer is disposed above the semiconductor layer. The saturation current suppression layer disposed above the first-conductivity-type layer includes a first deep layer and a JEFT portion. The base region is disposed above the saturation current suppression layer. The source region and the contact region are disposed above the region. Each of the trench gate structures has a gate trench, a gate insulation film, and a gate electrode. The second deep layer is disposed among the trench gate structures and is connected to the first deep layer.

Disclosed are a semiconductor device (1) including a MOSPET region and an integrated diode region, and a manufacturing method thereof. More particularly, a semiconductor device (1) including a silicon carbide (SiC) MOSPET region and an integrated Schottky bather diode that reduce forward voltage drop (Vf), device area, and switching oscillation resulting from parasitic inductance are disclosed.

This normally-off mode polarization super junction GaN-based field effect transistor has an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12 (0<x<1), an island-like undoped GaN layer 13, a p-type GaN layer 14, a p-type In.sub.yGa.sub.1-yN layer 15 (0<y<1), a gate electrode 16 on the p-type In.sub.yGa.sub.1-yN layer 15 and a source electrode 17 and a drain electrode 17 on the Al.sub.xGa.sub.1-xN layer 12. When the polarization charge amount of the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 and the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 13 is denoted as N.sub.PZ and the thickness of the Al.sub.xGa.sub.1-xN layer 12 is denoted as d, N.sub.PZ d?2.64?10.sup.14 [cm.sup.?2 nm] is satisfied.

A semiconductor device is provided. The semiconductor device includes a substrate, a first gate electrode, a second gate electrode, and an isolation structure. The first gate electrode is over the substrate and the second gate electrode is laterally adjacent thereto. The isolation structure is in contact with the first gate electrode and the second gate electrode.

A semiconductor device is provide. The device includes a first n type of layer, a second n type of layer, and an n+ type of region sequentially disposed on a first surface of a substrate. A trench is disposed on a side surface of the second n type of layer, a p type of region is disposed between the second n type of layer and the trench, and a gate electrode is disposed on a bottom surface of the trench. A source electrode is disposed on the n+ type of region and a drain electrode is disposed on a second surface of the substrate. The second n type of layer includes a first concentration layer, a second concentration layer, a third concentration layer, and a fourth concentration layer sequentially disposed on the first n type of layer.

According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of monocrystalline SiC, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, and an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.

This nitride semiconductor device is provided with: a depletion type transistor which comprises a first gate terminal, a first source terminal and a first drain terminal; and an enhancement type transistor which comprises a second gate terminal, a second source terminal and a second drain terminal. The second drain terminal is connected to the first source terminal; and the second source terminal is connected to the first gate terminal. The depletion type transistor comprises: an electron transit layer which is configured from a nitride semiconductor that contains aluminum in the crystal composition; and an electron supply layer which is formed on the electron transit layer and is configured from a nitride semiconductor that contains a larger amount of aluminum in the composition than the electron transit layer.