The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.

An integrated chemical sensor device includes a chemical sensor comprising at least one transistor and having an external sensing surface electrically coupled to a node of the at least one transistor. There is an initialization circuit connected to the base of the at least one transistor configured to set an operating point for the at least one transistor. There is a temperature sensor control circuit coupled to the chemical sensor circuit. The temperature sensor includes a temperature sensor, an analog-to-digital (A/D) converter coupled to the temperature sensor, and a proportional-to-absolute-temperature (PTAT) circuit configured to generate a PTAT reference voltage for temperature compensation. The temperature sensor control circuit is configured to compensate for a change in temperature of the at least one transistor.

A power element includes a substrate structure, an insulation layer, a dielectric layer, a transistor, and a plurality of zener diodes. The transistor is located in a transistor formation region of the substrate structure. The plurality of zener diodes are located in a circuit element formation region of the substrate structure and connected in series with each other. Each of the zener diodes includes a zener diode doping structure and a zener diode metal structure. The zener diode doping structure is formed on the insulation layer and is covered by the dielectric layer. The zener diode doping structure includes a P-type doped region and an N-type doped region that are in contact with each other. The zener diode metal structure is formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region.

The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.

A multi-transistor configuration including a first transistor having a first terminal that is configured to control the flow of current between, a second terminal of the first transistor and a third terminal of the first transistor; a second transistor, that is a bipolar junction transistor comprising a base terminal, an emitter terminal, and a collector terminal, wherein the third terminal of the first transistor and the collector terminal of the second transistor are electrically connected; and a first voltage source having a first terminal at a first voltage and a second terminal at a second voltage.

A method for producing a semiconductor device, the method includes, forming, on a substrate made from a semiconductor substance, at least one bipolar junction (BJ) transistor including a first terminal connected to a first well, the first well formed in the substrate and includes a first dopant having a first dopant concentration. At least one non-BJ transistor is formed on the substrate, the non-BJ transistor includes a second terminal connected to a second well, and the second well formed in the substrate and includes a second dopant having a same polarity as the first dopant. The first dopant concentration of the BJ transistor is higher than the second dopant concentration of the non-BJ transistor.

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

This application provides a process for making a circuit of a bipolar junction transistor (BJT). The switchable short in one implementation of the invention is formed in a semiconductor wafer. A collector region is formed in the semiconductor wafer and inside of the collector region, a first base region is formed. An emitter region is formed inside the base region to form the BJT. A drain region is also formed inside the base region adjacent to the emitter region. A gate is formed over a portion of the base region adjacent to the drain region and the emitter region. The gate is connected to the collection region.

An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

This application provides a process for making a circuit of a bipolar junction transistor (BJT). The switchable short in one implementation of the invention is formed in a semiconductor wafer. A collector region is formed in the semiconductor wafer and inside of the collector region, a first base region is formed. An emitter region is formed inside the base region to form the BJT. A drain region is also formed inside the base region adjacent to the emitter region. A gate is formed over a portion of the base region adjacent to the drain region and the emitter region. The gate is connected to the collection region.