Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer having a top surface and a side surface, a second terminal having a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further includes a contact positioned to overlap with the top surface and the side surface of the first raised semiconductor layer.

A method for rapidly gathering a sub-threshold swing from a thin film transistor is provided. The method includes: electrically connecting an operational amplifier and an anti-exponential component to a source terminal of the thin film transistor; performing a measuring process to the thin film transistor in which the measuring process is inputting multiple values of a gate voltage to a gate terminal, such that multiple values of an output voltage are correspondingly generated from the output terminal of the operational amplifier; and performing a fitting process to the output voltage corresponding to the thin film transistor in which the fitting process is fitting at least two of said multiple values of the output voltage to get the sub-threshold swing.

Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with thermal conductor and methods of manufacture. The structure includes: a base formed within a semiconductor substrate; a thermal conductive material under the base and extending to an underlying semiconductor material; an emitter on a first side of the base; and a collector on a second side of the base.

Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

Disclosed is a semiconductor structure including a device, such as a lateral heterojunction bipolar transistor (HBT), made up of a combination of at least three different semiconductor materials with different bandgap sizes for improved performance. In the device, a base layer of the base region can be positioned laterally between a collector layer of a collector region and an emitter layer of an emitter region and can be physically separated therefrom by buffer layers. The base layer can be made of a narrow bandgap semiconductor material, the collector layer and, optionally, the emitter layer can be made of a wide bandgap semiconductor material, and the buffer layers can be made of a semiconductor material with a bandgap between that of the narrow bandgap semiconductor material and the wide bandgap semiconductor material. Also disclosed herein is a method of forming the structure.

Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first base layer, a second base layer, a first terminal positioned between the first base layer and the second base layer, a second terminal, and a third terminal. The first base layer, the second base layer, and the first terminal are positioned between the second terminal and the third terminal. For example, the first terminal may be positioned in a vertical direction between the first and second base layers.

A structure for a lateral bipolar junction transistor is provided. The structure comprising an emitter including a first concentration of a first dopant. A collector including a second concentration of the first dopant, the first concentration of the first dopant may be different from the second concentration of the first dopant. An intrinsic base may be laterally arranged between the emitter and the collector, and an extrinsic base region may be above the intrinsic base. An emitter extension may be arranged adjacent to the emitter, whereby the emitter extension laterally extends under a portion of the extrinsic base region. A halo region may be arranged adjacent to the emitter extension, whereby the halo region laterally extends under another portion of the extrinsic base region.

Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.