The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Aspects of the disclosure provide an integrated circuit (IC) structure with a bipolar transistor stack within a substrate. The bipolar transistor stack may include: a collector, a base on the collector, and an emitter on a first portion of the base. A horizontal width of the emitter is less than a horizontal width of the base, and an upper surface of the emitter is substantially coplanar with an upper surface of the substrate. An extrinsic base structure is on a second portion of the base of the bipolar transistor stack, and horizontally adjacent the emitter. The extrinsic base structure includes an upper surface above the upper surface of the substrate.

The present disclosure relates to semiconductor structures and, more particularly, to gate controlled transistors and methods of manufacture. The structure includes: an emitter region; a collector region; base regions on opposing sides of the emitter region and the collector region; and a gate structure composed of a body region and leg regions, the body region being located between the base regions on opposing sides of the emitter region and the collector region, and the leg regions isolating the base regions from both the emitter region and the collector region.

Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.

Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.

One illustrative method of forming heterojunction bipolar devices includes, among other things, forming a first gate structure above an active semiconductor layer, forming a second gate structure adjacent a first side of the first gate structure, forming a third gate structure adjacent a second side of the first gate structure, forming an emitter of a bipolar transistor in the active semiconductor layer between the first gate structure and the second gate structure, forming a collector of the bipolar transistor in the active semiconductor layer between the first gate structure and the third gate structure, and forming a first base contact contacting the active region adjacent an end of the first gate structure, wherein a portion of the active semiconductor layer positioned under the first gate structure defines a base of the bipolar transistor.

The present disclosure relates to semiconductor structures and, more particularly, to gate controlled transistors and methods of manufacture. The structure includes: an emitter region; a collector region; base regions on opposing sides of the emitter region and the collector region; and a gate structure composed of a body region and leg regions, the body region being located between the base regions on opposing sides of the emitter region and the collector region, and the leg regions isolating the base regions from both the emitter region and the collector region.

One illustrative method of forming heterojunction bipolar devices includes, among other things, forming a first gate structure above an active semiconductor layer, forming a second gate structure adjacent a first side of the first gate structure, forming a third gate structure adjacent a second side of the first gate structure, forming an emitter of a bipolar transistor in the active semiconductor layer between the first gate structure and the second gate structure, forming a collector of the bipolar transistor in the active semiconductor layer between the first gate structure and the third gate structure, and forming a first base contact contacting the active region adjacent an end of the first gate structure, wherein a portion of the active semiconductor layer positioned under the first gate structure defines a base of the bipolar transistor.

A method for rapidly gathering a sub-threshold swing from a thin film transistor is provided. The method includes: electrically connecting an operational amplifier and an anti-exponential component to a source terminal of the thin film transistor; performing a measuring process to the thin film transistor in which the measuring process is inputting multiple values of a gate voltage to a gate terminal, such that multiple values of an output voltage are correspondingly generated from the output terminal of the operational amplifier; and performing a fitting process to the output voltage corresponding to the thin film transistor in which the fitting process is fitting at least two of said multiple values of the output voltage to get the sub-threshold swing.

A method of forming a lateral bipolar junction transistor (LBJT) that includes providing a germanium containing layer on a crystalline oxide layer, and patterning the germanium containing layer stopping on the crystalline oxide layer to form a base region. The method may further include forming emitter and collector extension regions on opposing sides of the base region using ion implantation, and epitaxially forming an emitter region and collector region on the crystalline oxide layer into contact with the emitter and collector extension regions. The crystalline oxide layer provides a seed layer for the epitaxial formation of the emitter and collector regions.