An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

A method of manufacturing a semiconductor device includes: forming an isolation region comprising a dielectric material on a substrate; forming a recess in the isolation region, wherein a thickness of the isolation region is reduced but greater than zero in the recess; forming a fill layer or layer stack including at least one of a semiconductor or metal on the isolation region and which conforms to the recess; forming a dishing prevention layer or layer stack on the fill layer or layer stack and which conforms to the recess; planarizing the dishing prevention layer or layer stack and the fill layer or layer stack to confine the dishing prevention layer or layer stack and the fill layer or layer stack to the recess, wherein the planarizing stops on the isolation region outside the recess; and forming one or more electrical contacts to the fill layer or layer stack confined to the recess.

A method of forming an active matrix pixel that includes forming a driver device including contact regions deposited using a low temperature deposition process on a first portion of an insulating substrate. An electrode of an organic light emitting diode is formed on a second portion of the insulating substrate. The electrode is in electrical communication to receive an output from the driver device. At least one passivation layer is formed over the driver device. A switching device comprising at least one amorphous semiconductor layer is formed on the at least one passivation layer over the driver device.

An SOI or PSOI device including a device structure having a plurality of doped semiconductor regions. One or more of the doped semiconductor regions is in electrical communication with one or more electrical terminals. The device further includes an insulator layer located between a bottom surface of the device structure and a handle wafer. The device has an insulator trench structure located between a side surface of the device structure and a lateral semiconductor region located laterally with respect to the device structure. The insulator layer and the insulator trench structure are configured to insulate the device structure from the handle wafer and the lateral semiconductor region, and the insulator trench structure includes a plurality of insulator trenches.

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with thermal conductor and methods of manufacture. The structure includes: a base formed within a semiconductor substrate; a thermal conductive material under the base and extending to an underlying semiconductor material; an emitter on a first side of the base; and a collector on a second side of the base.

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a collector contact and methods of manufacture. The structure includes: a lateral bipolar transistor which includes an emitter, a base and a collector; an emitter contact to the emitter; a base contact to the base; and a collector contact to the collector and extending to an underlying substrate underneath the collector.

A semiconductor device has a semiconductor substrate, at least one first transistor that has a mesa structure including one or more semiconductor layers, a first bump that overlaps the first transistor and extends in a first direction, and a second bump, in which the mesa structure has a first end portion on one end side in a second direction and a second end portion on the other end side in the second direction. The opening has a first opening end portion and a second opening end portion that are adjacent in the second direction. In plan view, the first opening end portion is closer to the second bump than the second opening end portion and the first end portion and the second end portion of the mesa structure are disposed between the first opening end portion and the second opening end portion.

Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region in a semiconductor substrate; a base region adjacent to the collector region; and an emitter extending above the base region and comprising semiconductor material and a hardmask surrounding a lower portion of the semiconductor material.