Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

A semiconductor device includes a semiconductor substrate; at least one first transistor, each first transistor including a mesa structure including one or more semiconductor layers; a first bump overlapping the first transistors and extending in a first direction; and a second bump. The mesa structure includes a first end portion at one end in a second direction and a second end portion at another end in the second direction. In plan view, an outer periphery of the first bump includes a first side and a second side extending in the first direction and arranged next to each other in the second direction. The first side is closer to the second bump than the second side in the second direction. The first end portion and the second end portion of the mesa structure are between the first side and the second side.

A disclosed structure includes a bipolar junction transistor (BJT) and a method of forming the structure. The structure includes a semiconductor layer on an insulator layer. The BJT includes a base region positioned laterally between emitter and collector regions. The emitter region includes an emitter portion of the semiconductor layer and an emitter semiconductor layer, which is within an emitter cavity in the insulator layer, which extends through an emitter opening in the emitter portion, and which covers the top of the emitter portion. The collector region includes a collector portion of the semiconductor layer and a collector semiconductor layer, which is within a collector cavity in the insulator layer, which extends through a collector opening in the collector portion, and which covers the top of the collector portion. Optionally, the structure also includes air pockets within the emitter and collector cavities.

Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer, a second terminal having a second raised semiconductor layer, and a base layer positioned laterally between the first raised semiconductor layer and the second raised semiconductor layer. The structure further includes a spacer positioned laterally positioned between the first raised semiconductor layer and the base layer. The spacer includes a dielectric material and an airgap surrounded by the dielectric material.

The disclosure provides a bipolar transistor structure with multiple bases, and related methods. A bipolar transistor structure includes a first emitter/collector (E/C) material above an insulator. The first E/C material has first sidewall and a second sidewall over the insulator. A first base is above the insulator adjacent the first sidewall of the first E/C material. A second base is above the insulator adjacent the second sidewall of the first E/C material. A second E/C material is above the insulator and adjacent the first base. A width of the first base between the first E/C material and the second E/C material is less than a width of the first E/C material, and the first base protrudes horizontally outward from an end of the first E/C material and an end of the second E/C material.

Embodiments provide a method for manufacturing a bipolar junction transistor. The method comprises a step of providing a layer stack, the layer stack comprising a semiconductor substrate having a trench isolation, a base contact layer stack, wherein the base contact layer stack comprises a recess forming an emitter window, lateral spacers arranged on sidewalls of the emitter window, the lateral spacers isolating a base contact layer of the base contact layer stack; and a base layer arranged in the emitter window on the semiconductor substrate, wherein the base layer at least partially protrudes under the lateral spacers. The method further comprises a step of providing an isolation layer on the base layer.

Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

A method of manufacturing a semiconductor device includes: forming an isolation region comprising a dielectric material on a substrate; forming a recess in the isolation region, wherein a thickness of the isolation region is reduced but greater than zero in the recess; forming a fill layer or layer stack including at least one of a semiconductor or metal on the isolation region and which conforms to the recess; forming a dishing prevention layer or layer stack on the fill layer or layer stack and which conforms to the recess; planarizing the dishing prevention layer or layer stack and the fill layer or layer stack to confine the dishing prevention layer or layer stack and the fill layer or layer stack to the recess, wherein the planarizing stops on the isolation region outside the recess; and forming one or more electrical contacts to the fill layer or layer stack confined to the recess.

A semiconductor structure including a substrate, a BJT, a first interconnect structure and a second interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The BJT is located at the first side. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. The first interconnect structure is located at the first side and electrically connected to the base. The second interconnect structure is located at the second side and electrically connected to the collector. The first interconnect structure further extends to the second side. The first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side. The semiconductor structure can have better overall performance.

The present disclosure relates to semiconductor structures and, more particularly, to a substrate with trap rich and low resistivity regions and methods of manufacture. The structure includes: a high resistivity semiconductor substrate; an active device over the high resistivity semiconductor substrate; and a low resistivity region floating in the high resistivity semiconductor substrate and which is below the active device.