A power converter includes: at least one pair of first and second semiconductor devices including multiple first and second semiconductor chips, having first and second switching elements providing upper and lower arms, and multiple first and second main terminals having at least one of multiple first and second high potential terminals and multiple first and second low potential terminals; and a bridging member providing an upper and lower coupling portion, together with the first low and second high potential terminals. The first and second semiconductor chips are arranged in line symmetry with respect to first and second axes and in line symmetry with the second axis as a symmetry axis to differentiate the arrangement of the second low potential terminal with respect to the second high potential terminal from the arrangement of the first low potential terminal with respect to the first high potential terminal.

A semiconductor device has a cell part and a terminal part set in the device. The terminal part encloses the cell part. The semiconductor device includes a first electrode, a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, and an insulating layer. The first semiconductor layer is formed above the first electrode. The second semiconductor layer is provided in an upper portion of the first semiconductor layer, and has an impurity concentration profile along a vertical direction including a plurality of peaks. The insulating layer is provided on the second semiconductor layer.

A semiconductor device is provided, which includes a semiconductor chip; a first current input/output portion that is electrically connected to the semiconductor chip; a second current input/output portion that is electrically connected to the semiconductor chip; three or more conducting portions provided with the semiconductor chip, between the first current input/output portion and the second current input/output portion; and a current path portion having a path through which current is conducted to each of the three or more conducting portions, wherein the current path portion includes a plurality of slits.

A silicon carbide (SiC) metal oxide semiconductor (MOS) power device is disclosed which includes an SiC drain semiconductor region, an SiC drift semiconductor region coupled to the SiC drain semiconductor region, an SiC base semiconductor region coupled to the SiC drift semiconductor region, an SiC source semiconductor region coupled to the SiC base semiconductor region, a source electrode coupled to the SiC source semiconductor region, a drain electrode coupled to the SiC drain semiconductor region, a gate electrode, wherein voltage of the gate electrode with respect to the SiC base semiconductor region is less than or equal to about 12 V and thickness of the dielectric material is such that the electric field in the dielectric material is about 4 MV/cm when said gate voltage is about 12 V.

A semiconductor device (300) comprising: a doped semiconductor substrate (302); an epitaxial layer (304), disposed on top of the substrate, the epitaxial layer having a lower concentration of dopant than the substrate; a switching region disposed on top of the epitaxial layer; and a contact diffusion (350) disposed on top of the epitaxial layer, the contact diffusion having a higher concentration of dopant than the epitaxial layer; wherein the epitaxial layer forms a barrier between the contact diffusion and the substrate.

An apparatus includes a drift region formed over the substrate, a body region over the substrate, a first well region formed over the drift region, a collector region formed in the first well region, an emitter region formed in the body region, a first body contact formed in the body region, a first gate situated between the collector region and the emitter region, a second well region formed over the substrate, a drain region formed in the second well region, wherein the drain region and the emitter region are electrically connected to each other, a source region formed in the second well region, wherein the source region and the first body contact are electrically connected to each other, and a second gate situated between the drain region and the source region, wherein the second gate and the first gate are electrically connected to each other.

In this patent application, a new Metal Oxide Semiconductor MOS planar cell design concept is proposed. The inventive power semiconductor includes a planar cell forming a horizontal channel and a plurality of trenches, which are arranged orthogonally to the plane of the planar cells. A second p base layer is introduced which extends perpendicularly deeper than the source region and laterally to the same distance/extent as the source region. Therefore, a vertical channel is prevented from forming in the trench regions while allowing the horizontal channels to form. This is extremely important in order to avoid significant issues (i.e. shifts in Vth) encountered in prior art IGBT designs. The new cell concept adopts planar MOS channel and Trench technology in a single MOS cell structure. The new design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability), and processability (narrow mesa design rules, reliable planar process compatibility) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as Silicon Carbide SiC. Furthermore, the device is easy to manufacture, because the inventive design can be manufactured based on a self-aligned process with minimum number of masks, with the potential of additionally applying enhancement layers and/or reverse conducting type of structures.

The technology of this disclosure relates to an IGBT chip integrating a temperature sensor, and relates to the field of power device technologies, to improve accuracy of temperature monitoring of the IGBT chip. The IGBT chip integrating the temperature sensor includes a cell region, an emitter pad, a gate pad, a gate finger structure, a temperature sensing module, and a conductive shielding structure. The emitter pad is electrically connected to emitters of a plurality of IGBT cells. The gate finger structure is connected between the gate pad and gates of the plurality of IGBT cells. The temperature sensing module includes a temperature sensor, an anode pad, a cathode pad, and a metal lead. The temperature sensor and at least a part of the metal lead are located in the gate finger structure and are insulated from the gate finger structure.

Provided is a semiconductor device including a semiconductor chip which has a main surface, a high potential region which is formed in a surface layer portion of the main surface, a low potential region which is formed in the surface layer portion of the main surface at an interval from the high potential region, a first conductive type drift region which is formed in a region between the high potential region and the low potential region in the surface layer portion of the main surface, and a first conductive type resurf region which is formed partially in a surface layer portion of the drift region such as to expose a part of a region which serves as a current path in the drift region from the main surface and which has an impurity concentration higher than that of the drift region.

A semiconductor device includes: a first electrode; a first semiconductor layer on the first electrode in a diode region; a second semiconductor layer on the first electrode in an IGBT region; a semiconductor layer on the first and second semiconductor layers, a first upper layer of the semiconductor layer in the diode region including a first region adjacent to the IGBT region and a second region separated from the IGBT region, an impurity concentration being less in the first region than in the second region; a third semiconductor layer on the semiconductor layer; a fourth semiconductor layer of the third semiconductor layer in the IGBT region; a third electrode extending in a direction from the fourth semiconductor layer toward the semiconductor layer; and an insulating film between the second electrode and each of the third semiconductor layer, the semiconductor layer, and the third electrode.