A semiconductor structure includes a substrate, a stacked structure on the substrate, an insulating layer on the stacked structure, a passivation layer on the insulating layer, and a contact structure through the passivation layer and the insulating layer and directly contacting the stacked structure. The insulating layer has an extending portion protruding from a sidewall of the passivation layer and adjacent to a surface of the stacked structure directly contacting the contact structure.

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of gates disposed on the quantum well stack; and a top gate at least partially disposed on the plurality of gates such that the plurality of gates are at least partially disposed between the top gate and the quantum well stack.

A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer.

A semiconductor device includes a first and a second nitride-based semiconductor layers, a source electrode, a drain electrode, a gate electrode, and a first and a second stress modulation layers. The first nitride-based semiconductor layer has a first thickness. The second nitride-based semiconductor layer has a bandgap less than a bandgap of the first nitride-based semiconductor layer to form a heterojunction therebetween. The second nitride-based semiconductor layer has a second thickness, and a ratio of the first thickness to the second thickness is in a range from 0.5 to 5. The first and the second stress modulation layers provide a first and a second drift regions of the second nitride-based semiconductor layer with stress, respectively, resulting in induction of a first and a second 2DHG regions within the first and the second drift regions, respectively.

A compound semiconductor device includes a carrier supply layer, a channel layer disposed over the carrier supply layer and configured to include InGaAs, and an etching stopper layer disposed over the channel layer, and configured to include a first layer disposed over the channel layer and configured to include In.sub.x1Ga.sub.1-x1P, and a second layer disposed over the first layer and configured to include In.sub.x2Ga.sub.1-x2P, wherein x1 is greater than 0 and less than or equal to 1, x2 is greater than or equal to 0 and less than 1, and x1 is greater than x2.

A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer containing Ga on a substrate; forming a first layer on the first nitride semiconductor layer; forming a second layer on the first layer; forming an opening in which the first nitride semiconductor layer is exposed in the second layer and the first layer; forming a second nitride semiconductor layer of a first conductivity type on a surface, exposed in the opening, of the first nitride semiconductor layer; removing the second layer using an acidic solution; and after removing the second layer, forming an electrode on the second nitride semiconductor layer. A first etching rate of the first layer for the acidic solution is lower than a second etching rate of the second layer for the acidic solution.

A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.

Gallium nitride (GaN) layer transfer for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A first layer including gallium and nitrogen is over a first region of the substrate, the first layer having a gallium-polar orientation with a top crystal plane consisting of a gallium face. A second layer including gallium and nitrogen is over a second region of the substrate, the second layer having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.

High electron mobility transistors are provided which comprise a III-Nitride semiconductor layer comprising a III-Nitride semiconductor, in contact with a gallium oxide semiconductor layer comprising gallium oxide, forming an interface therebetween.