A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

Provided are a semiconductor structure and manufacturing method thereof, the semiconductor comprising: a base (10), wherein the base (10) comprises strip trenches (101) arranged parallelly; and a heterojunction structure (11) located on bottom walls and sidewalls of the strip trenches and on the base other than the strip trenches, wherein regions of the heterojunction structure located on the bottom walls and on the base other than the strip trenches are polarized regions, regions of the heterojunction structure on the sidewalls are non-polarized regions, and the polarized regions contain carriers; the heterojunction structure comprises a source region (11a) and a drain region (11b) respectively located at both ends of each of the strip trenches, and a gate region (11c) between the source region and the drain region; and the carriers between the source region and the drain region are confined to flow in each of the polarized regions.

A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a replacement channel composed of a III-V compound semiconductor material in a doped layer of a III-V compound semiconductor substrate. The replacement channel may be formed by removing a portion of the doped layer located directly below a dummy gate stack that has been removed. A III-V compound semiconductor material may be grown in the removed the portion to form the replacement channel and a gate stack may be formed on the replacement channel.

A field effect transistor includes a III-Nitride channel layer, a III-Nitride doped cap layer on the channel layer, a source electrode in contact with the III-Nitride cap layer, a drain electrode in contact with the III-Nitride cap layer, a gate electrode located between the source and the drain electrodes, and a gate dielectric layer between the gate electrode and the III-Nitride undoped channel layer, wherein the cap layer is doped to provide mobile holes, and wherein the gate dielectric layer comprises a layer of AlN in contact with the channel layer.

A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of nanowires positioned above and parallel to a top surface of the substrate, wherein the plurality of nanowires comprises channel regions and source/drain regions positioned on each of both sides of the channel regions; a gate stack positioned surrounding the channel regions; and a magnetic storage structure positioned above a drain region of the plurality of nanowires and positioned adjacent to the gate stack. The magnetic storage structure comprises a bottom ferromagnetic layer positioned above the drain region and having a variable magnetic polarity, a tunnel barrier layer positioned on the bottom ferromagnetic layer, and a top ferromagnetic layer positioned on the tunnel barrier layer and having a fixed magnetic polarity.

A semiconductor device includes a graphene film disposed on a substrate and formed of atomic layers of graphene that are stacked, a source electrode and a drain electrode disposed on the graphene film, and a gate electrode disposed on the graphene film between the source electrode and the drain electrode with a gate insulator film interposed between the gate electrode and the graphene film, wherein a first number of the atomic layers of the graphene film in a source region where the source electrode is located and a drain region where the drain electrode is located is greater than a second number of the atomic layers of the graphene film in a channel region where the gate electrode is located.