A wafer bonding technique to fabricate GaN devices is disclosed. In this technique, a GaN layer (or a GaN stack including at least one GaN layer) is fabricated on a first substrate (e.g., a silicon substrate) and has a high quality surface with a dislocation density less than 10.sup.10/cm.sup.2. The assembly of the first substrate and the GaN layer is then bonded to a second substrate (e.g., a carbide substrate or an AlN substrate) by coupling the high quality surface to the second substrate. The high quality of the GaN surface in contact with the carbide substrate creates a good thermal contact. The first substrate is etched away to expose a GaN surface for further processing, such as electrode formation.

A stacked body includes: a substrate made of silicon carbide and having a first main surface forming an angle of 20° or less with a carbon plane; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of silicon carbide forming the substrate. In an exposed surface of the graphene film as seen in plan view, 10 or less regions are present per 1 mm.sup.2, the exposed surface being a main surface opposite to the substrate, and the regions each including 10 or more graphene layers and having a circumcircle with a diameter of 5 μm or more and 100 μm or less. Accordingly, the stacked body is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.

In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.

Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase V.sub.t. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease V.sub.t. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies V.sub.t. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

A semiconductor device that includes a fin structure, and a channel epitaxial wrap around layer at each end of a channel portion of the fin structure. The semiconductor device also includes a gate structure including a gate dielectric having gate edge portions in direct contact with the channel epitaxial wrap around layer. A middle portion of the gate dielectric is in direct contact with a central channel portion of the fin structure between the two ends of the channel portion of the fin structure. Source and drain regions are present on opposing sides of the channel portion of the fin structure.

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm.sup.2/Vs to the diamond lattice at 100 kPa and 300K, and wherein the n-type donor atoms are introduced to the lattice through ion tracks.

Memory devices, methods of manufacturing the same, and methods of accessing the same are provided. In one embodiment, the memory device may include a substrate, a back gate formed on the substrate, and a transistor. The transistor may include fins formed on opposite sides of the back gate on the substrate and a gate stack formed on the substrate and intersecting the fins. The memory device may further include a back gate dielectric layer formed on side and bottom surfaces of the back gate. The back gate dielectric layer may have a thickness reduced portion at a region facing the fins on one side of the gate stack.

A stacked structure includes: an insulating substrate; a graphene film that is formed on the insulating substrate; and a protective film that is formed on the graphene film and is made of a transition metal oxide, which is, for example, Cr.sub.2O.sub.3. Thereby, at the time of transfer of the graphene, polymeric materials such as a resist are prevented from directly coming into contact with the graphene and nonessential carrier doping on the graphene caused by a polymeric residue of the resist is suppressed.

A semiconductor structure, device, or N-polar Ill-nitride vertical field effect transistor. The structure, device, or transistor includes a current blocking layer and an aperture region. The current blocking layer and aperture region are comprised of the same material The current blocking layer and aperture region are formed by polarization engineering and not doping or implantation. A method of making a semiconductor structure, device, or Ill-nitride vertical transistor. The method includes obtaining, growing, or forming a functional bilayer comprising a barrier layer and a two-dimensional electron gas-containing layer. The functional bilayer is not formed via a regrowth step.

A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.