In an embodiment, a Group III nitride-based transistor device, includes a first Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length l.sub.d, and 0 nm≤l.sub.d≤200 nm.

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Provided are semiconductor devices and methods of manufacturing the same. A semiconductor device may include a source, a drain, a semiconductor element between the source and the drain, and a graphene layer that is provided on the source and the semiconductor element and is spaced apart from the drain. Surfaces of the source and the drain are substantially co-planar with a surface of the semiconductor element. The semiconductor element may be spaced apart from the source and may contact the drain. The graphene layer may have a planar structure. A gate insulating layer and a gate may be provided on the graphene layer. The semiconductor device may be a transistor. The semiconductor device may have a barristor structure. The semiconductor device may be a planar type graphene barristor.

To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.

An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.

A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance.

A substrate includes: a support substrate having a first main surface and a surface layer region which includes at least the first main surface and is formed of any one material selected from the group consisting of boron nitride, molybdenum disulfide, tungsten disulfide, niobium disulfide, and aluminum nitride; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of the material forming the surface layer region. Accordingly, the substrate is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.

In some embodiments, a microelectronic sensor includes an open-gate pseudo-conductive high-electron mobility transistor and used for biometric authentication of a user. The transistor comprises a substrate, on which a multilayer hetero-junction structure is deposited. This hetero-junction structure comprises a buffer layer and a barrier layer, both grown from III-V single-crystalline or polycrystalline semiconductor materials. A two-dimensional electron gas (2DEG) conducting channel is formed at the interface between the buffer and barrier layers and provides electron current in the system between source and drain electrodes. The source and drain contacts, which maybe either ohmic or non-ohmic (capacitively-coupled), are connected to the formed 2DEG channel and to electrical metallizations, the latter are placed on top of the transistor and connect it to the sensor system. The metal gate electrode is placed between the source and drain areas on or above the barrier layer, which may be recessed or grown to a specific thickness. An optional dielectric layer is deposited on top of the barrier layer.

A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source material coupled to a first end of the first and second channel layers, a drain material coupled to a second end of the first and second channel layers, a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer and a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

Field effect transistors (FET) including quantum layers. A FET may include a substrate, and an oxide layer disposed over the substrate. The oxide layer may include a first section and a second section positioned adjacent the first section. The FET may also include a first quantum layer disposed over the first section of the oxide layer, and a second quantum layer disposed over the second section of the oxide layer, and a first segment of the first quantum layer. Additionally, the FET may include a drain region disposed directly over a second segment the first quantum layer. The second segment of the first quantum layer may be positioned adjacent the first segment of the first quantum layer. The FET may further include a source region disposed over the second quantum layer, and a channel region formed over the second quantum layer, between the drain region and the source region.