A semiconductor structure and a manufacturing method thereof are provided in the present disclosure. The semiconductor structure includes a semiconductor substrate; a plurality of stacked structures and a plurality of isolation structures on the semiconductor substrate, wherein the stacked structures are spaced apart each other, and each of the isolation structures are located between adjacent stacked structures; each of the stacked structures comprises a nucleation layer and a first epitaxial layer from bottom to top; and a heterojunction structure on the plurality of stacked structures, wherein the heterojunction structure is distributed over an entire surface, and an air gap is formed between the heterojunction structure and each of the isolation structures.

A method for manufacturing an epitaxial substrate includes the steps of: epitaxially growing a group III nitride semiconductor layer on a substrate; removing the substrate from a growth furnace; irradiating a surface of the group III nitride semiconductor layer with ultraviolet light while exposing the surface to an atmosphere containing oxygen; and measuring a sheet resistance value of the group III nitride semiconductor layer.

A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction.

Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

This disclosure provides a semiconductor epitaxial structure and a semiconductor device. The semiconductor epitaxial structure includes a channel layer, a composite barrier layer, and a doping layer. The doping layer is disposed on the composite barrier layer, the channel layer is disposed on a side of the composite barrier layer that faces away from the doping layer, the composite barrier layer includes a digital alloy barrier layer and an AlGaN barrier layer that are disposed in a laminated manner, and the digital alloy barrier layer includes one or more AlN layers. The semiconductor epitaxial structure provided in this disclosure effectively prevents Mg ions in a p-GaN layer from diffusing to the barrier layer and the channel layer to affect density and mobility of two-dimensional electronic gas and cause a problem of an increase in on resistance.

Described herein are devices and methods that utilize three-dimensional topological semimetals (including Dirac, Weyl and nodal line) that may be useful in advanced electronic devices. The Fermi level in three dimensional topological semimetals can be significantly shifted in energy when forming a heterojunction with a semiconductor or metal. This has unintended and sometimes negative consequences for device performance. Described herein are designs and methods to modify the heterostructures to either suppress Fermi level movement or to produce an intentional shift to allow for the use of these improved semimetal devices.

A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

According to one embodiment, a semiconductor device includes first, second, third nitride members, first, second, third electrodes, and a first insulating member. The first nitride member includes a first face along a first plane, a second face along the first plane, and a third face. The third face is connected with the first and second faces between the first and second faces. The third face crosses the first plane. The first face overlaps a part of the first nitride member. The second nitride member includes a first nitride region provided at the first face. The third nitride member includes a first nitride portion provided at the second face. The first electrode includes a first connecting portion. The second electrode includes a second connecting portion. The third electrode includes a first electrode portion. The first insulating member includes a first insulating region.