A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

Embodiments of this application relate to the field of semiconductor technologies, and provide a composite substrate and a preparation method thereof, a semiconductor device, and an electronic device. The composite substrate includes a bearer layer, a silicon carbide layer, and at least one epitaxial layer. The silicon carbide layer is disposed on the bearer layer and bonded to the bearer layer, and a material of the silicon carbide layer includes monocrystal silicon carbide. The at least one epitaxial layer is disposed on a side that is of the silicon carbide layer and that is away from the bearer layer.

A high electron mobility transistor includes a stack of layers including a passivation layer and a heterojunction including a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at the interface thereof, one surface of the passivation layer being in contact with the first semiconductor layer; a source metal contact and/or a drain metal contact and a gate electrode; an n+ doped zone situated inside the heterojunction; the source metal contact and/or the drain metal contact being positioned at the level of a recess formed in the stack of layers, the source metal contact and/or said drain metal contact having a thickness defined by an upper face and a lower face substantially parallel to the plane of the layers, the upper face being planar, the lower face being in contact with the n+ doped zone and below the interface between the first and second semiconductor layers.

According to one embodiment, a semiconductor device includes a first crystal region, a second crystal region, a third crystal region, and a fourth crystal region. The first crystal region includes magnesium and Al.sub.x1Ga.sub.1-x1N (0≤x1<1). The second crystal region includes Al.sub.x2Ga.sub.1-x2N (0<x2≤1). The third crystal region is provided between the first crystal region and the second crystal region. The third crystal region includes oxygen and Al.sub.x3Ga.sub.1-x3N (0≤x3≤1 and x3<x2). The fourth crystal region is provided between the third crystal region and the second crystal region. The fourth crystal region includes Al.sub.x4Ga.sub.1-x4N (0≤x4<1 and x4<x2).

An N-polar III-N high-electron mobility transistor device can include a III-N channel layer over an N-face of a III-N backbarrier, wherein a compositional difference between the channel layer and the backbarrier causes a 2DEG channel to be induced in the III-N channel layer adjacent to the interface between the III-N channel layer and the backbarrier. The device can further include a p-type III-N layer over the III-N channel layer and a thick III-N cap layer over the p-type III-N layer. The III-N cap layer can cause an increase in the charge density of the 2DEG channel directly below the cap layer, and the p-type III-N layer can serve to prevent a parasitic 2DEG from forming in the III-N cap layer.

A nitride semiconductor device includes a substrate, a drift layer and a block layer sequentially provided above the substrate, a gate opening penetrating through a block layer and reaching a drift layer, an electron transit layer and an electron supply layer sequentially provided above the block layer and along the inner surface of the gate opening, a gate electrode provided to cover the gate opening, a source opening penetrating through an electron supply layer and an electron transit layer and reaching the block layer, a source electrode provided in the source opening, and a drain electrode on the rear surface side of the substrate. Seen in a plan view, at least part of an outline of an end of the gate opening in the longitudinal direction follows an arc or an elliptical arc.