A semiconductor device, includes: a first semiconductor chip including a first semiconductor substrate; and a second semiconductor chip including a second semiconductor substrate, wherein the first semiconductor substrate has a first substrate main surface and a first substrate back surface facing opposite directions in a first direction, and includes a first region and a second region disposed on the first substrate main surface, wherein the first semiconductor chip includes: a first MOSFET of a first type structure formed to include the first region; and a control circuit formed to include the second region, wherein the second semiconductor chip includes a second MOSFET of a second type structure formed to include the second semiconductor substrate, and wherein the second type structure is different from the first type structure.

A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.

The present disclosure relates to semiconductor structures and, more particularly, to poly gate extension source to body contact structures and methods of manufacture. The structure includes: a substrate having a doped region; a gate structure over the doped region, the gate structure having a main body and a gate extension region; and a body contact region straddling over the gate extension region and remote from the main body of the gate structure.

Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes stacked first and second PNP bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and an NMOS transistor connected in series with the stacked first and second PNP bipolar transistors and the second node. An emitter and a base of the second PNP bipolar transistor are connected to a collector of the first PNP bipolar transistor. A gate terminal of the NMOS transistor is connected to a source terminal of the NMOS transistor. Other embodiments are also described.

The present disclosure relates to semiconductor structures and, more particularly, to poly gate extension source to body contact structures and methods of manufacture. The structure includes: a substrate having a doped region; a gate structure over the doped region, the gate structure having a main body and a gate extension region; and a body contact region straddling over the gate extension region and remote from the main body of the gate structure.

A structure includes channel regions located between source/drain regions, and a polysilicon gate structure including a plurality of gate fingers, each extending over a corresponding channel region. Each gate finger includes first and second rectangular portions extending in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along a second axis. This offset causes each source/drain region to have a first section with a first length along the second axis, and a second section with a second length along the second axis, greater than the first length. A single column of contacts having a first width along the second axis is provided in the first section of each source/drain region, and a single column of contacts having a second width along the second axis, greater than the first width, is provided in the second section of each source/drain region.

A rectifying device 100 includes: at least one MOSFET (PMOSFET 20) having a gate terminal 26a, a drain terminal 25a, and a well terminal 23a that are interconnected; an AC signal generation source 80 that generates an AC signal to cause the at least one MOSFET to operate in a voltage region including a weak inversion region, and supplies the AC signal to a source terminal 24a of the MOSFET; and a capacitative element C connected to the drain terminal 25a of the MOSFET. As a rectifying element, a MOSFET that is driven even in a weak inversion region by short-circuiting the gate, drain, and well, and so have low rectification loss, and small leakage current is used; therefore, rectifying devices that are highly efficient, have low leakage current, can cope with high frequency, and thus are suitable for energy harvesting technologies to collect very weak energy are constituted.

A printed circuit board (PCB) land pad for a three-pin metal-oxide-semiconductor field-effect transistor (MOSFET) component comprises four pads with a split pad for a drain terminal of the MOSFET component. The PCB land pad comprises: a first pad to connect a gate terminal of the MOSFET component to a PCB; a second pad to connect a source terminal of the MOSFET component to the PCB; a third pad corresponding to connect a drain terminal of the MOSFET component to the PCB; and a fourth pad to connect the drain terminal of the MOSFET component to the PCB.

An example welding-type power supply includes: a transformer having a primary winding and first and second secondary windings; an input circuit configured to provide an input voltage to the primary winding of the transformer; first, second, third, and fourth switching elements, and a control circuit configured to: control the first, second, third, and fourth switching elements to selectively output a positive or negative output voltage without a separate rectifier stage by selectively controlling ones of the first, second, third, and fourth switching elements based on a commanded output voltage polarity and an input voltage polarity to the transformer; and prior to changing from a first output voltage polarity to a second output voltage polarity, controlling the first, second, third, and fourth switching elements to reverse the power flow to return reactive energy to an input circuit via the transformer.

One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.